<> <> <> <> <<>> DIRECTORY CD, CoreClasses, CoreCreate, CoreCompose, CoreOps, IO, PW, PWCore; CrossRAMDecoderImpl: CEDAR PROGRAM IMPORTS CoreCompose, IO, PW, PWCore EXPORTS = BEGIN OPEN CoreCompose; <> Decoder: ROPE = RegisterStructureProc[name: "Decoder", proc: CreateDecoder]; CreateDecoder: StructureProc = { cellType _ CreateRecordCell[ name: Decoder, context: context, public: CreateWires[context, "Vdd, Gnd, AccessB, AdrBit[seq: addressDecoderBits], nAdrBit[seq: addressDecoderBits], Word[seq: 4*rowQuads]"], onlyInternal: CreateWires[context, "nDecode[seq: 2*rowQuads]"], instances: LIST [ [type: CreateStructure[name: "DecoderLeftColumn", context: context]], [type: CreateStructure[name: "DecoderAndPlane", context: context], actual: "AdrBit: AdrBit[start: 0, len: andDecoderBits], nAdrBit: nAdrBit[start: 0, len: andDecoderBits], ch2: Vdd"], [type: CreateStructure[name: "DecoderRightColumn", context: context]], [type: CreateStructure[name: "DecoderLogicColumn", context: context], actual: "TreeSelect: [AdrBit[addressDecoderBits-1], nAdrBit[addressDecoderBits-1]]"] ] ]; PWCore.SetAbutX[cellType: cellType]; }; <> <> DecoderAndPlane: ROPE = RegisterStructureProc[name: "DecoderAndPlane", proc: CreateDecoderAndPlane]; CreateDecoderAndPlane: StructureProc = { rowPairs: INT _ GetInt[context, $rowPairs]; andDecoderBits: INT _ GetInt[context, $andDecoderBits]; DecoderAndPlaneLayout: PROC[] RETURNS [obj: PW.Object] = { DecoderSelect: PW.XYFunction ={ oddWord: BOOL _ PW.ODD[y]; oddBit: BOOL _ PW.XthBitOfN[x, y]; index: INT _ 2*(IF oddBit THEN 1 ELSE 0)+(IF oddWord THEN 1 ELSE 0); resultingOb _ SELECT index FROM 0 => dec0, 1 => dec1, 2 => dec0FlipY, 3 => dec1FlipY, ENDCASE => ERROR; }; design: CD.Design _ NARROW[GetRef[context, $sourceCDDesign]]; dec0: PW.Object _ PW.Get[design, "DecoderZero"]; dec1: PW.Object _ PW.Get[design, "DecoderOne"]; dec0FlipY: PW.Object _ PW.FlipY[design, dec0]; dec1FlipY: PW.Object _ PW.FlipY[design, dec1]; obj _ PW.MapFunction[NIL, DecoderSelect, 0, andDecoderBits-1, 0, rowPairs-1]; }; cellType _ CreateRecordCell[ name: DecoderAndPlane, context: context, public: CreateWires[context, "Vdd, Gnd, AdrBit[seq: andDecoderBits], nAdrBit[seq: andDecoderBits], nDecode[seq: rowPairs]"] ]; PWCore.SetLayout[cellType: cellType, cdObject: DecoderAndPlaneLayout[]]; }; <> <> AdrBit: ROPE = RegisterStructureProc[name: "AdrBit", proc: CreateDecoderBit]; CreateDecoderBit: StructureProc = { adrRope: ROPE _ IF zero THEN "nAdrBit" ELSE "AdrBit"; zero: BOOL _ GetBool[context, $zero]; cellType _ CreateRecordCell[ name: IO.PutFR["Decoder%g", IO.rope[IF zero THEN "Zero" ELSE "One"]], context: context, public: CreateWires[context, "Vdd, Gnd, AdrBit, nAdrBit, nDecode, nStackTop, nStackBottom"], instances: LIST [ [type: CreateTransistor[name: "Transistor", type: pE], actual: IO.PutFR["gate: %g, ch1: Vdd, ch2: nDecode", IO.rope[adrRope]]], [type: CreateTransistor[name: "Transistor", type: nE], actual: IO.PutFR["gate: %g, ch1: nStackTop, ch2: nStackBottom", IO.rope[adrRope]]]] ]; PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]]; }; <> <> <> <> <> <<[] _ CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd", "AdrBit", "nAdrBit", "nDecode", "nStackTop", "nStackBottom"]];>> <<[] _ CreateCellInstance[design: design, in: cell, type: CoreTransistor.Create[args: NEW[CoreTransistor.TransistorRec _ [type: pE]]], bind: IO.PutFR["gate: %g, ch1: Vdd, ch2: nDecode", IO.rope[adrRope]]];>> <<[] _ CreateCellInstance[design: design, in: cell, type: CoreTransistor.Create[args: NEW[CoreTransistor.TransistorRec _ [type: nE]]], bind: IO.PutFR["gate: %g, ch1: nStackTop, ch2: nStackBottom", IO.rope[adrRope]]];>> <<};>> <<};>> <<>> <> DecoderLeftColumn: ROPE = RegisterStructureProc[name: "DecoderLeftColumn", proc: CreateDecoderLeftColumn]; CreateDecoderLeftColumn: StructureProc = { cellType _ CreateSequenceCell[ name: DecoderLeftColumn, baseCell: CreateStructure[name: DecoderLeftPair, context: context], count: GetInt[context: context, prop: $rowQuads]]; PWCore.SetArrayY[cellType: cellType]; }; <> DecoderLeftPair: ROPE = RegisterStructureProc[name: "DecoderLeftPair", proc: CreateDecoderLeftPair]; CreateDecoderLeftPair: StructureProc = { cellType _ CreateRecordCell[ name: DecoderLeftPair, context: context, public: CreateWires[context, "Vdd, Gnd"], instances: LIST [ [type: CreateStructure[name: "DecoderLeft", context: context]], [type: CreateStructure[name: "DecoderLeftFlipY", context: context]]]]; PWCore.SetAbutY[cellType: cellType]; }; <> DecoderLeft: ROPE = RegisterStructureProc[name: "DecoderLeft", proc: CreateDecoderLeft]; CreateDecoderLeft: StructureProc = { cellType _ CreateRecordCell[ name: DecoderLeft, context: context, public: CreateWires[context, "Vdd, Gnd"]]; PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]]; }; <> DecoderRightColumn: ROPE = RegisterStructureProc[name: "DecoderRightColumn", proc: CreateDecoderRightColumn]; CreateDecoderRightColumn: StructureProc = { cellType _ CreateSequenceCell[ name: DecoderRightColumn, baseCell: CreateStructure[name: "DecoderRightPair", context: context], count: GetInt[context: context, prop: $rowQuads], sequencePorts: "nDecode"]; PWCore.SetArrayY[cellType: cellType]; }; <> DecoderRightPair: ROPE = RegisterStructureProc[name: "DecoderRightPair", proc: CreateDecoderRightPair]; CreateDecoderRightPair: StructureProc = { instances: LIST OF CoreClasses.CellInstance; inst1, inst2: CoreClasses.CellInstance; cellType _ CreateRecordCell[ name: DecoderRightPair, context: context, public: CreateWires[context, "Vdd, nDecode[seq: 2]"], instances: LIST [ [actual: "nDecode: nDecode[0]", type: CreateStructure[name: "DecoderRight", context: context]], [actual: "nDecode: nDecode[1]", type: CreateStructure[name: "DecoderRight", context: context]]]]; instances _ NARROW [cellType.data, CoreClasses.RecordCellType].instances; inst1 _ instances.first; inst2 _ instances.rest.first; PWCore.SetLayout[ cellType, PW.AbutX[NIL, PWCore.GateWay[inst1], PW.FlipY[NIL, PWCore.GateWay[inst2]]] ]; }; <> <> <> <> <> <> <<[actual: "nDecode: nDecode[0]",>> <> <<[actual: "nDecode: nDecode[1]",>> <> <> <<};>> <> DecoderRight: ROPE = RegisterStructureProc[name: "DecoderRight", proc: CreateDecoderRight]; CreateDecoderRight: StructureProc = { cellType _ CreateRecordCell[ name: DecoderRight, context: context, public: CreateWires[context, "Vdd, nDecode"]]; PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]]; }; <> DecoderLogicColumn: ROPE = RegisterStructureProc[name: "DecoderLogicColumn", proc: CreateDecoderLogicColumn]; CreateDecoderLogicColumn: StructureProc = { cellType _ CreateSequenceCell[ name: DecoderLogicColumn, baseCell: CreateStructure[name: DecoderLogicPair, context: context], count: GetInt[context: context, prop: $rowQuads], sequencePorts: "nDecode, Word"]; PWCore.SetArrayY[cellType: cellType]; }; <> DecoderLogicPair: ROPE = RegisterStructureProc[name: "DecoderLogicPair", proc: CreateDecoderLogicPair]; CreateDecoderLogicPair: StructureProc = { cellType _ CreateRecordCell[ name: DecoderLogicPair, context: context, public: CreateWires[context, "Vdd, Gnd, AccessB, TreeSelect[seq: 2], nDecode[seq: 2], Word[seq: 4]"], instances: LIST [ [actual: "Word: Word[start: 0, len: 2], nDecode: nDecode[0]", type: CreateStructure[name: "DecoderLogic", context: context]], [actual: "Word: Word[start: 2, len: 2], nDecode: nDecode[1]", type: CreateStructure[name: "DecoderLogicFlipY", context: context]]]]; PWCore.SetAbutY[cellType: cellType]; }; <> DecoderLogicFlipY: ROPE = RegisterStructureProc[name: "DecoderLogicFlipY", proc: CreateDecoderLogicFlipY]; CreateDecoderLogicFlipY: StructureProc = { <> <> <> <> <> PWCore.SetFlipY[cellType: cellType]; }; <> DecoderLogic: ROPE = RegisterStructureProc[name: "DecoderLogic", proc: CreateDecoderLogic]; CreateDecoderLogic: StructureProc = { cellType _ CreateSequenceCell[ name: DecoderLogic, baseCell: CreateStructure[name: WordDriver, context: context], count: 2, sequencePorts: "TreeSelect, Word"]; PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]]; }; <> WordDriver: ROPE = RegisterStructureProc[name: "WordDriver", proc: CreateWordDriver]; CreateWordDriver: StructureProc = { cellType _ CreateRecordCell[ name: WordDriver, context: context, public: CreateWires[context, "Vdd, Gnd, AccessB, TreeSelect, Word, nDecode"], onlyInternal: CreateWires[context, "nTreeDecode, Decode, nWord, WordStack"], instances: LIST [ [actual: "Input: nTreeDecode, Output: Decode", type: CreateStructure[name: "Inverter", context: context]], [actual: "Input: nWord, Output: Word", type: CreateStructure[name: "Inverter", context: context]], [actual: "gate: Decode, ch1: nWord, ch2: WordStack", type: CreateTransistor[name: "Transistor", type: nE]], [actual: "gate: AccessB, ch1: WordStack, ch2: Gnd", type: CreateTransistor[name: "Transistor", type: nE]], [actual: "gate: TreeSelect, ch1: nDecode, ch2: nTreeDecode", type: CreateTransistor[name: "Transistor", type: nE]], [actual: "gate: AccessB, ch1: Vdd, ch2: nWord", type: CreateTransistor[name: "Transistor", type: pE]], [actual: "gate: TreeSelect, ch1: Vdd, ch2: nTreeDecode", type: CreateTransistor[name: "Transistor", type: pE]]]]; }; END.