CrossRAMDecoderImpl.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Barth, September 26, 1985 12:41:41 pm PDT
Louis Monier October 24, 1985 7:56:58 pm PDT
DIRECTORY CD, CoreClasses, CoreCreate, CoreCompose, CoreOps, IO, PW, PWCore;
CrossRAMDecoderImpl:
CEDAR
PROGRAM
IMPORTS CoreCompose, IO, PW, PWCore
EXPORTS =
BEGIN OPEN CoreCompose;
rowQuads, addressDecoderBits: INT
Decoder: ROPE = RegisterStructureProc[name: "Decoder", proc: CreateDecoder];
CreateDecoder: StructureProc = {
cellType ← CreateRecordCell[
name: Decoder,
context: context,
public: CreateWires[context, "Vdd, Gnd, AccessB, AdrBit[seq: addressDecoderBits], nAdrBit[seq: addressDecoderBits], Word[seq: 4*rowQuads]"],
onlyInternal: CreateWires[context, "nDecode[seq: 2*rowQuads]"],
instances:
LIST [
[type: CreateStructure[name: "DecoderLeftColumn", context: context]],
[type: CreateStructure[name: "DecoderAndPlane", context: context],
actual: "AdrBit: AdrBit[start: 0, len: andDecoderBits],
nAdrBit: nAdrBit[start: 0, len: andDecoderBits], ch2: Vdd"],
[type: CreateStructure[name: "DecoderRightColumn", context: context]],
[type: CreateStructure[name: "DecoderLogicColumn", context: context],
actual: "TreeSelect: [AdrBit[addressDecoderBits-1], nAdrBit[addressDecoderBits-1]]"]
]
];
PWCore.SetAbutX[cellType: cellType];
};
rowPairs, andDecoderBits: INT
Ports: Vdd, Gnd, AdrBit[0..andDecoderBits), nAdrBit[0..andDecoderBits), nDecode[0..rowPairs)
DecoderAndPlane: ROPE = RegisterStructureProc[name: "DecoderAndPlane", proc: CreateDecoderAndPlane];
CreateDecoderAndPlane: StructureProc = {
rowPairs: INT ← GetInt[context, $rowPairs];
andDecoderBits: INT ← GetInt[context, $andDecoderBits];
DecoderAndPlaneLayout:
PROC[]
RETURNS [obj:
PW.Object] = {
DecoderSelect:
PW.XYFunction ={
oddWord: BOOL ← PW.ODD[y];
oddBit: BOOL ← PW.XthBitOfN[x, y];
index: INT ← 2*(IF oddBit THEN 1 ELSE 0)+(IF oddWord THEN 1 ELSE 0);
resultingOb ←
SELECT index
FROM
0 => dec0,
1 => dec1,
2 => dec0FlipY,
3 => dec1FlipY,
ENDCASE => ERROR;
};
design: CD.Design ← NARROW[GetRef[context, $sourceCDDesign]];
dec0: PW.Object ← PW.Get[design, "DecoderZero"];
dec1: PW.Object ← PW.Get[design, "DecoderOne"];
dec0FlipY: PW.Object ← PW.FlipY[design, dec0];
dec1FlipY: PW.Object ← PW.FlipY[design, dec1];
obj ← PW.MapFunction[NIL, DecoderSelect, 0, andDecoderBits-1, 0, rowPairs-1];
};
cellType ← CreateRecordCell[
name: DecoderAndPlane,
context: context,
public: CreateWires[context,
"Vdd, Gnd,
AdrBit[seq: andDecoderBits], nAdrBit[seq: andDecoderBits], nDecode[seq: rowPairs]"]
];
PWCore.SetLayout[cellType: cellType, cdObject: DecoderAndPlaneLayout[]];
};
zero: BOOL
Ports: Vdd, Gnd, AdrBit, nAdrBit, nDecode, nStackTop, nStackBottom
AdrBit: ROPE = RegisterStructureProc[name: "AdrBit", proc: CreateDecoderBit];
CreateDecoderBit: StructureProc = {
adrRope: ROPE ← IF zero THEN "nAdrBit" ELSE "AdrBit";
zero: BOOL ← GetBool[context, $zero];
cellType ← CreateRecordCell[
name: IO.PutFR["Decoder%g", IO.rope[IF zero THEN "Zero" ELSE "One"]],
context: context,
public: CreateWires[context, "Vdd, Gnd, AdrBit, nAdrBit, nDecode, nStackTop, nStackBottom"],
instances:
LIST [
[type: CreateTransistor[name: "Transistor", type: pE],
actual: IO.PutFR["gate: %g, ch1: Vdd, ch2: nDecode", IO.rope[adrRope]]],
[type: CreateTransistor[name: "Transistor", type: nE],
actual: IO.PutFR["gate: %g, ch1: nStackTop, ch2: nStackBottom", IO.rope[adrRope]]]]
];
PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
};
CreateDecoderBit: PROC [design: Design, zero: BOOL] RETURNS [cell: CellType] = {
name: ROPE ← IO.PutFR["Decoder%g", IO.rope[IF zero THEN "Zero" ELSE "One"]];
IF (cell ← FetchCell[design, name])=NIL THEN {
adrRope: ROPE ← IF zero THEN "nAdrBit" ELSE "AdrBit";
cell ← CreateRecordCell[design: design, name: name, attribute: [$GenLayout, $Get]];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd", "AdrBit", "nAdrBit", "nDecode", "nStackTop", "nStackBottom"]];
[] ← CreateCellInstance[design: design, in: cell, type: CoreTransistor.Create[args: NEW[CoreTransistor.TransistorRec ← [type: pE]]], bind: IO.PutFR["gate: %g, ch1: Vdd, ch2: nDecode", IO.rope[adrRope]]];
[] ← CreateCellInstance[design: design, in: cell, type: CoreTransistor.Create[args: NEW[CoreTransistor.TransistorRec ← [type: nE]]], bind: IO.PutFR["gate: %g, ch1: nStackTop, ch2: nStackBottom", IO.rope[adrRope]]];
};
};
Ports: Vdd, Gnd
DecoderLeftColumn: ROPE = RegisterStructureProc[name: "DecoderLeftColumn", proc: CreateDecoderLeftColumn];
CreateDecoderLeftColumn: StructureProc = {
cellType ← CreateSequenceCell[
name: DecoderLeftColumn,
baseCell: CreateStructure[name: DecoderLeftPair, context: context],
count: GetInt[context: context, prop: $rowQuads]];
PWCore.SetArrayY[cellType: cellType];
};
Ports: Vdd, Gnd
DecoderLeftPair: ROPE = RegisterStructureProc[name: "DecoderLeftPair", proc: CreateDecoderLeftPair];
CreateDecoderLeftPair: StructureProc = {
cellType ← CreateRecordCell[
name: DecoderLeftPair,
context: context,
public: CreateWires[context, "Vdd, Gnd"],
instances:
LIST [
[type: CreateStructure[name: "DecoderLeft", context: context]],
[type: CreateStructure[name: "DecoderLeftFlipY", context: context]]]];
PWCore.SetAbutY[cellType: cellType];
};
Ports: Vdd, Gnd
DecoderLeft: ROPE = RegisterStructureProc[name: "DecoderLeft", proc: CreateDecoderLeft];
CreateDecoderLeft: StructureProc = {
cellType ← CreateRecordCell[
name: DecoderLeft,
context: context,
public: CreateWires[context, "Vdd, Gnd"]];
PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
};
Ports: Vdd, nDecode[0..2*rowQuads)
DecoderRightColumn: ROPE = RegisterStructureProc[name: "DecoderRightColumn", proc: CreateDecoderRightColumn];
CreateDecoderRightColumn: StructureProc = {
cellType ← CreateSequenceCell[
name: DecoderRightColumn,
baseCell: CreateStructure[name: "DecoderRightPair", context: context],
count: GetInt[context: context, prop: $rowQuads],
sequencePorts: "nDecode"];
PWCore.SetArrayY[cellType: cellType];
};
Ports: Vdd, nDecode[0..2)
DecoderRightPair: ROPE = RegisterStructureProc[name: "DecoderRightPair", proc: CreateDecoderRightPair];
CreateDecoderRightPair: StructureProc = {
instances: LIST OF CoreClasses.CellInstance;
inst1, inst2: CoreClasses.CellInstance;
cellType ← CreateRecordCell[
name: DecoderRightPair,
context: context,
public: CreateWires[context, "Vdd, nDecode[seq: 2]"],
instances:
LIST [
[actual: "nDecode: nDecode[0]",
type: CreateStructure[name: "DecoderRight", context: context]],
[actual: "nDecode: nDecode[1]",
type: CreateStructure[name: "DecoderRight", context: context]]]];
instances ← NARROW [cellType.data, CoreClasses.RecordCellType].instances;
inst1 ← instances.first; inst2 ← instances.rest.first;
PWCore.SetLayout[
cellType,
PW.AbutX[NIL, PWCore.GateWay[inst1], PW.FlipY[NIL, PWCore.GateWay[inst2]]]
];
};
CreateDecoderRightPair: StructureProc = {
cellType ← CreateRecordCell[
name: DecoderRightPair,
context: context,
public: CreateWires[context, "Vdd, nDecode[seq: 2]"],
instances: LIST [
[actual: "nDecode: nDecode[0]",
type: CreateStructure[name: "DecoderRight", context: context]],
[actual: "nDecode: nDecode[1]",
type: CreateStructure[name: "DecoderRightFlipY", context: context]]]];
PWCore.SetAbutX[cellType: cellType];
};
Ports: Vdd, nDecode
DecoderRight: ROPE = RegisterStructureProc[name: "DecoderRight", proc: CreateDecoderRight];
CreateDecoderRight: StructureProc = {
cellType ← CreateRecordCell[
name: DecoderRight,
context: context,
public: CreateWires[context, "Vdd, nDecode"]];
PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
};
Ports: Vdd, Gnd, AccessB, TreeSelect[0..2), Word[0..4*rowQuads), nDecode[0..2*rowQuads)
DecoderLogicColumn: ROPE = RegisterStructureProc[name: "DecoderLogicColumn", proc: CreateDecoderLogicColumn];
CreateDecoderLogicColumn: StructureProc = {
cellType ← CreateSequenceCell[
name: DecoderLogicColumn,
baseCell: CreateStructure[name: DecoderLogicPair, context: context],
count: GetInt[context: context, prop: $rowQuads],
sequencePorts: "nDecode, Word"];
PWCore.SetArrayY[cellType: cellType];
};
Ports: Vdd, Gnd, AccessB, TreeSelect[0..2), Word[0..4), nDecode[0..2)
DecoderLogicPair: ROPE = RegisterStructureProc[name: "DecoderLogicPair", proc: CreateDecoderLogicPair];
CreateDecoderLogicPair: StructureProc = {
cellType ← CreateRecordCell[
name: DecoderLogicPair,
context: context,
public: CreateWires[context, "Vdd, Gnd, AccessB, TreeSelect[seq: 2], nDecode[seq: 2], Word[seq: 4]"],
instances:
LIST [
[actual: "Word: Word[start: 0, len: 2], nDecode: nDecode[0]",
type: CreateStructure[name: "DecoderLogic", context: context]],
[actual: "Word: Word[start: 2, len: 2], nDecode: nDecode[1]",
type: CreateStructure[name: "DecoderLogicFlipY", context: context]]]];
PWCore.SetAbutY[cellType: cellType];
};
Ports: Vdd, Gnd, AccessB, TreeSelect[0..2), Word[0..2), nDecode
DecoderLogicFlipY: ROPE = RegisterStructureProc[name: "DecoderLogicFlipY", proc: CreateDecoderLogicFlipY];
CreateDecoderLogicFlipY: StructureProc = {
cellType ← CreateSequenceCell[ -- identity cell???
name: DecoderLogicFlipY,
baseCell: CreateStructure[name: DecoderLogic, context: context],
count: 2,
sequencePorts: "TreeSelect", "Word"];
PWCore.SetFlipY[cellType: cellType];
};
Ports: Vdd, Gnd, AccessB, TreeSelect[0..2), Word[0..2), nDecode
DecoderLogic: ROPE = RegisterStructureProc[name: "DecoderLogic", proc: CreateDecoderLogic];
CreateDecoderLogic: StructureProc = {
cellType ← CreateSequenceCell[
name: DecoderLogic,
baseCell: CreateStructure[name: WordDriver, context: context],
count: 2,
sequencePorts: "TreeSelect, Word"];
PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
};
Ports: Vdd, Gnd, AccessB, TreeSelect, Word, nDecode
WordDriver: ROPE = RegisterStructureProc[name: "WordDriver", proc: CreateWordDriver];
CreateWordDriver: StructureProc = {
cellType ← CreateRecordCell[
name: WordDriver,
context: context,
public: CreateWires[context, "Vdd, Gnd, AccessB, TreeSelect, Word, nDecode"],
onlyInternal: CreateWires[context, "nTreeDecode, Decode, nWord, WordStack"],
instances:
LIST [
[actual: "Input: nTreeDecode, Output: Decode",
type: CreateStructure[name: "Inverter", context: context]],
[actual: "Input: nWord, Output: Word",
type: CreateStructure[name: "Inverter", context: context]],
[actual: "gate: Decode, ch1: nWord, ch2: WordStack",
type: CreateTransistor[name: "Transistor", type: nE]],
[actual: "gate: AccessB, ch1: WordStack, ch2: Gnd",
type: CreateTransistor[name: "Transistor", type: nE]],
[actual: "gate: TreeSelect, ch1: nDecode, ch2: nTreeDecode",
type: CreateTransistor[name: "Transistor", type: nE]],
[actual: "gate: AccessB, ch1: Vdd, ch2: nWord",
type: CreateTransistor[name: "Transistor", type: pE]],
[actual: "gate: TreeSelect, ch1: Vdd, ch2: nTreeDecode",
type: CreateTransistor[name: "Transistor", type: pE]]]];
};
END.