CrossRAMDataBufferImpl.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Barth, September 20, 1985 2:12:36 pm PDT
Louis Monier October 28, 1985 8:34:19 am PST
DIRECTORY CD, CoreCompose, IO, PW, PWCore, Rope;
CrossRAMDataBufferImpl:
CEDAR
PROGRAM
IMPORTS CoreCompose, PW, PWCore
EXPORTS =
BEGIN OPEN CoreCompose;
DataBuffer: ROPE = RegisterStructureProc[name: "DataBuffer", proc: CreateDataBuffer];
CreateDataBuffer: StructureProc = {
columnOcts: INT ← GetInt[context, $columnOcts];
cellType ← CreateSequenceCell[
name: DataBuffer,
baseCell: CreateStructure[name: "DataBufferBit", context: context],
count: columnOcts,
sequencePorts: "Bit, nBit, DataB"];
PWCore.SetArrayX[cellType: cellType];
};
Ports: Vdd, Gnd, WriteB, nWriteB, ReadB, nReadB, DataB, Select[0..select), Bit[0..select), nBit[0..select)
DataBufferBit: ROPE = RegisterStructureProc[name: "DataBufferBit", proc: CreateDataBufferBit];
CreateDataBufferBit: StructureProc = {
cellType ← CreateRecordCell[
name: DataBufferBit,
context: context,
public: CreateWires[context,
"Vdd, Gnd, WriteB, nWriteB, ReadB, nReadB, DataB,
Select[SEQ:select], Bit[SEQ:select], nBit[SEQ:select]"],
instances:
LIST [
[type: CreateStructure[name: "DataBufferOct", context: context]],
[type: CreateStructure[name: "DecoderStitch", context: context]]
]];
PWCore.SetAbutX[cellType: cellType];
};
Ports: Vdd, Gnd, WriteB, nWriteB, ReadB, nReadB, DataB, Select[0..select), Bit[0..select), nBit[0..select)
DataBufferOct: ROPE = RegisterStructureProc[name: "DataBufferOct", proc: CreateDataBufferOct];
CreateDataBufferOct: StructureProc = {
cellType ← CreateRecordCell[
name: DataBufferOct,
context: context,
public: CreateWires[context,
"Vdd, Gnd, WriteB, nWriteB, ReadB, nReadB, DataB,
Select[SEQ:select], Bit[SEQ:select], nBit[SEQ:select]"],
onlyInternal: CreateWires[context, "Buffer, nBuffer"],
instances:
LIST [
[type: CreateStructure[name: "BitLineConnectSeq", context: context]],
[type: CreateStructure[name: "DataBufferMux", context: context]],
[type: CreateStructure[name: "DataBufferMuxBit", context: context]],
[type: CreateStructure[name: "BitDrive", context: context]]
]];
PWCore.SetAbutY[cellType: cellType];
};
Ports: Gnd, Select[0..select), Bit[0..select), nBit[0..select), Buffer, nBuffer
DataBufferMuxBit: ROPE = RegisterStructureProc[name: "DataBufferMuxBit", proc: CreateDataBufferMux];
CreateDataBufferMux: StructureProc = {
select: INT ← GetInt[context, $select];
static: BOOL ← GetBool[context, $static];
cellType ← CreateRecordCell[
name: DataBufferMuxBit,
context: context,
public: CreateWires[context, "Gnd, Buffer, nBuffer, Select[seq: select], Bit[seq: select], nBit[seq: select]"],
instances:
LIST [
[type: CreateStructure[name: "BitMuxEnd", context: context],
-- just a PW.Get
actual: "Select: Select[0], Bit: Bit[0], nBit: nBit[0]"],
[type: CreateStructure[name: "BitMuxSeq", context: context],
actual: "Select: Select[start: 1, len: select-1], Bit: Bit[start: 1, len: select-1], nBit: nBit[start: 1, len: select-1]"]]];
PWCore.SetAbutX[cellType: cellType];
};
BitMuxSeq: ROPE = RegisterStructureProc[name: "BitMuxSeq", proc: CreateBitMuxSeq];
CreateBitMuxSeq: StructureProc = {
select: INT ← GetInt[context, $select];
cellType ← CreateSequenceCell[
name: BitMuxSeq,
baseCell: CreateStructure[name: "BitMux", context: context], -- just a PW.Get
count: select-1,
sequencePorts: "Select, Bit, nBit"];
PWCore.SetArrayX[cellType: cellType];
};
Ports: Gnd, Select, Bit, nBit, Buffer, nBuffer
BitMuxBit: ROPE = RegisterStructureProc[name: "BitMuxBit", proc: CreateBitMuxBit];
CreateBitMuxBit: StructureProc = {
static: BOOL ← GetBool[context, $static];
cellType ← CreateRecordCell[
name: BitMuxBit,
context: context,
public: CreateWires[context, "Gnd, Select, Bit, nBit, Buffer, nBuffer"],
instances:
LIST [
[type: CreateTransistor[name: "Transistor", type: nE],
actual: "gate: Select, ch1: Bit, ch2: Buffer"],
[type: CreateTransistor[name: "Transistor", type: nE],
actual: "gate: Select, ch1: nBit, ch2: nBuffer"]]
];
};
Ports: Gnd, Select[0..select), Bit[0..select), nBit[0..select)
DataBufferMux: ROPE = RegisterStructureProc[name: "DataBufferMux", proc: CreateDataBufferMuxSelect];
CreateDataBufferMuxSelect: StructureProc = {
select: INT ← GetInt[context, $select];
DataBufferMuxLayout:
PROC[]
RETURNS [obj:
PW.Object] = {
DataBufferMuxSelect:
PW.XYFunction ={
resultingOb ←
SELECT
TRUE
FROM
y>x => BitSelNoPoly,
y=x => BitSelContact,
y<x => BitSelPoly,
ENDCASE => ERROR;
};
design: CD.Design ← NARROW[GetRef[context, $sourceCDDesign]];
BitSelNoPoly: PW.Object ← PW.Get[design, "BitSelNoPoly"];
BitSelContact: PW.Object ← PW.Get[design, "BitSelContact"];
BitSelPoly: PW.Object ← PW.Get[design, "BitSelPoly"];
obj ← PW.MapFunction[NIL, DataBufferMuxSelect, 0, select, 0, select];
};
cellType ← CreateRecordCell[
name: DataBufferMux,
context: context,
public: CreateWires[context, "Gnd, Select[seq: select], Bit[seq: select], nBit[seq: select]"]
];
PWCore.SetLayout[cellType: cellType, cdObject: DataBufferMuxLayout[]];
};
CreateDataBufferMuxSelect: PUBLIC PROC [design: Design, select: NAT] RETURNS [cell: CellType] = {
bitSel: CellType ← CreateBitSel[design: design];
muxCellType[BitSelNoPoly] ← CreateIdentityCell[design: design, name: "BitSelNoPoly", baseCell: bitSel, attribute: [$GenLayout, $Get]];
muxCellType[BitSelContact] ← CreateIdentityCell[design: design, name: "BitSelContact", baseCell: bitSel, attribute: [$GenLayout, $Get]];
muxCellType[BitSelPoly] ← CreateBitSelPoly[design: design];
cell ← CoreMapFunction.Create[
name: name,
publicWire: CoreOps.CreateRecordWire[components: LIST [
CoreOps.CreateAtomWire[name: "Gnd"],
CoreOps.CreateSequenceWire[name: "Select", base: CoreOps.CreateAtomWire[], count: select],
CoreOps.CreateSequenceWire[name: "Bit", base: CoreOps.CreateAtomWire[], count: select],
CoreOps.CreateSequenceWire[name: "nBit", base: CoreOps.CreateAtomWire[], count: select]]],
args: muxCellType];
CoreOps.InsertCellType[design: design, cellType: cell];
PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, $MapFn]];
};
BitSelNoPoly: NAT = 0;
BitSelContact: NAT = 1;
BitSelPoly: NAT = 2;
MuxSelect: CoreMapFunction.XYFn = {
IF y>x THEN RETURN[BitSelNoPoly];
IF y=x THEN RETURN[BitSelContact];
IF y<x THEN RETURN[BitSelPoly];
};
Ports: Vdd, Gnd, WriteB, nWriteB, ReadB, nReadB, DataB, Buffer, nBuffer
BitDrive: ROPE = RegisterStructureProc[name: "BitDrive", proc: CreateBitDrive];
CreateBitDrive: StructureProc = {
cellType ← CreateRecordCell[
name: BitDrive,
context: context,
public: CreateWires[context, "Vdd, Gnd, WriteB, nWriteB, ReadB, nReadB, DataB, Buffer, nBuffer"],
onlyInternal: CreateWires[context, "ndatab"],
instances:
LIST [
[type: CreateStructure[name: "Inverter", context: context],
actual: "Input: DataB, Output: ndatab"],
[type: CreateStructure[name: "TristateBuffer", context: context],
actual: "nInput: nBuffer, Drive: ReadB, nDrive: nReadB, Output: DataB"],
[type: CreateStructure[name: "TristateBuffer", context: context],
actual: "nInput: DataB, Drive: WriteB, nDrive: nWriteB, Output: nBuffer"],
[type: CreateStructure[name: "TristateBuffer", context: context],
actual: "nInput: ndatab, Drive: WriteB, nDrive: nWriteB, Output: Buffer"]]];
PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
};
Ports: Gnd, Select, Bit, nBit
CreateBitSel: PROC [design: Design] RETURNS [cell: CellType] = {
name: ROPE ← "BitSel";
IF (cell ← FetchCell[design, name])=NIL THEN {
cell ← CreateRecordCell[design: design, name: name];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Gnd", "Select", "Bit", "nBit"]];
};
};
Ports: Gnd, Select, Bit, nBit, OtherSelect
CreateBitSelPoly: PROC [design: Design] RETURNS [cell: CellType] = {
name: ROPE ← "BitSelPoly";
IF (cell ← FetchCell[design, name])=NIL THEN {
cell ← CreateRecordCell[design: design, name: name, attribute: [$GenLayout, $Get]];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Gnd", "Select", "Bit", "nBit", "OtherSelect"]];
};
};
BitLineConnectSeq: ROPE = RegisterStructureProc[name: "BitLineConnectSeq", proc: CreateBitLineConnectSeq];
CreateBitLineConnectSeq: StructureProc = {
select: INT ← GetInt[context, $select];
cellType ← CreateSequenceCell[
name: BitLineConnectSeq,
baseCell: CreateStructure[name: "BitLineConnect", context: context],
count: select,
sequencePorts: "Bit, nBit"];
PWCore.SetArrayX[cellType: cellType];
};
Ports: Gnd, Bit, nBit
BitLineConnect: ROPE = RegisterStructureProc[name: "BitLineConnect", proc: CreateBitLineConnect];
CreateBitLineConnect: StructureProc = {
cellType ← CreateRecordCell[
name: BitLineConnect,
context: context,
public: CreateWires[context, "Gnd, Bit, nBit"]];
PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
};
Ports: Vdd, Gnd, WriteB, nWriteB, ReadB, nReadB, Select[0..select)
DecoderStitch: ROPE = RegisterStructureProc[name: "DecoderStitch", proc: CreateDecoderStitch];
CreateDecoderStitch: StructureProc = {
select: INT ← GetInt[context, $select];
cellType ← CreateRecordCell[
name: DecoderStitch,
context: context,
public: CreateWires[context, "Vdd, Gnd, WriteB, nWriteB, ReadB, nReadB, Select[seq: select]"]];
PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
};
END.