CrossRAMBottom.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Barth, November 7, 1985 4:44:40 pm PST
Louis Monier October 23, 1985 4:50:52 pm PDT
Bertrand Serlet November 15, 1985 3:54:40 pm PST
DIRECTORY Core, CoreCompose, CoreFlatten, CoreProperties, PWCore, Rosemary, Sinix;
CrossRAMBottom:
CEDAR
PROGRAM
IMPORTS CoreCompose, CoreFlatten, CoreProperties, PWCore, Rosemary, Sinix =
BEGIN OPEN CoreCompose;
columnOcts, addressDecoderBits: INT
Bottom:
ROPE = RegisterStructureProc[name: "Bottom", proc: CreateBottom];
CreateBottom: StructureProc = {
cellType ← CreateRecordCell[
name: Bottom,
context: context,
public: CreateWires[context, "Vdd, nPrechargeB, AccessB, Bit[SEQ:8*columnOcts], nBit[SEQ:8*columnOcts]"],
instances:
LIST [
[type: CreateStructure[name: "BottomDecoderLeft", context: context]],
[type: CreateStructure[name: "DecoderSeq", context: context]],
[type: CreateStructure[name: "BottomDecoderRight", context: context]],
[actual: "nPrechargeB1: nPrechargeB, nPrechargeB2: nPrechargeB",
type: CreateStructure[name: "Precharge", context: context]],
[type: CreateStructure[name: "BottomRight", context: context]]]];
IF GetBool[context, $PWCore] THEN PWCore.SetAbutX[cellType: cellType];
IF GetBool[context, $Sinix] THEN [] ← Sinix.ExtractObj[PWCore.GetLayout[cellType]];
};
BottomDecoderLeft:
ROPE = RegisterStructureProc[name: "BottomDecoderLeft", proc: CreateBottomDecoderLeft];
CreateBottomDecoderLeft: StructureProc = {
cellType ← CreateRecordCell[
name: BottomDecoderLeft,
context: context,
public: CreateWires[context, "Vdd"]];
IF GetBool[context, $PWCore] THEN PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
IF GetBool[context, $Sinix] THEN [] ← Sinix.ExtractObj[PWCore.GetLayout[cellType]];
};
Ports: Vdd
DecoderSeq:
ROPE = RegisterStructureProc[name: "DecoderSeq", proc: CreateDecoderSeq];
CreateDecoderSeq: StructureProc = {
cellType ← CreateSequenceCell[
name: DecoderSeq,
baseCell: CreateStructure[name: "BottomDecoder", context: context],
count: GetInt[context: context, prop: $addressDecoderBits]];
IF GetBool[context, $PWCore] THEN PWCore.SetArrayX[cellType: cellType];
IF GetBool[context, $Sinix] THEN [] ← Sinix.ExtractObj[PWCore.GetLayout[cellType]];
};
BottomDecoder:
ROPE = RegisterStructureProc[name: "BottomDecoder", proc: CreateBottomDecoder];
CreateBottomDecoder: StructureProc = {
cellType ← CreateRecordCell[
name: BottomDecoder,
context: context,
public: CreateWires[context, "Vdd"]];
IF GetBool[context, $PWCore] THEN PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
IF GetBool[context, $Sinix] THEN [] ← Sinix.ExtractObj[PWCore.GetLayout[cellType]];
};
BottomDecoderRight:
ROPE = RegisterStructureProc[name: "BottomDecoderRight", proc: CreateBottomDecoderRight];
CreateBottomDecoderRight: StructureProc = {
cellType ← CreateRecordCell[
name: BottomDecoderRight,
context: context,
public: CreateWires[context, "Vdd, nPrechargeB, AccessB"]];
IF GetBool[context, $PWCore] THEN PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
IF GetBool[context, $Sinix] THEN [] ← Sinix.ExtractObj[PWCore.GetLayout[cellType]];
Ports: Vdd, nPrechargeB1, nPrechargeB2, Bit[0..8*columnOcts), nBit[0..8*columnOcts)
Precharge:
ROPE = RegisterStructureProc[name: "Precharge", proc: CreatePrecharge];
CreatePrecharge: StructureProc = {
cellType ← CreateSequenceCell[
name: Precharge,
baseCell: CreateStructure[name: PrechargeOctStitch, context: context],
count: GetInt[context: context, prop: $columnOcts],
sequencePorts: "Bit, nBit"];
IF GetBool[context, $PWCore] THEN PWCore.SetArrayX[cellType: cellType];
IF GetBool[context, $Sinix] THEN [] ← Sinix.ExtractObj[PWCore.GetLayout[cellType]];
};
PrechargeOctStitch:
ROPE = RegisterStructureProc[name: "PrechargeOctStitch", proc: CreatePrechargeOctStitch];
CreatePrechargeOctStitch: StructureProc = {
cellType ← CreateRecordCell[
name: PrechargeOctStitch,
context: context,
public: CreateWires[context, "Vdd, nPrechargeB1, nPrechargeB2, Bit[SEQ:8], nBit[SEQ:8]"],
instances:
LIST [
[type: CreateStructure[name: "PrechargeOct", context: context]],
[actual: "VddWell: Vdd",
type: CreateStructure[name: "PrechargeStich", context: context]]
]];
IF GetBool[context, $PWCore] THEN PWCore.SetAbutX[cellType: cellType];
IF GetBool[context, $Sinix] THEN [] ← Sinix.ExtractObj[PWCore.GetLayout[cellType]];
};
Ports: Vdd, nPrechargeB1, nPrechargeB2, Bit[0..8), nBit[0..8)
PrechargeOct:
ROPE = RegisterStructureProc[name: "PrechargeOct", proc: CreatePrechargeOct];
CreatePrechargeOct: StructureProc = {
cellType ← CreateSequenceCell[
name: PrechargeOct,
baseCell: CreateStructure[name: "PrechargeSlice", context: context],
count: 8,
sequencePorts: "Bit, nBit"];
IF GetBool[context, $PWCore] THEN PWCore.SetArrayX[cellType: cellType];
IF GetBool[context, $Sinix] THEN [] ← Sinix.ExtractObj[PWCore.GetLayout[cellType]];
};
PrechargeSlice:
ROPE ← RegisterStructureProc[name: "PrechargeSlice", proc: CreatePrechargeSlice];
CreatePrechargeSlice: StructureProc = {
peTranType: Core.CellType ← CreateTransistor[name: "Transistor", type: pE];
cellType ← CreateRecordCell[
name: PrechargeSlice,
context: context,
public: CreateWires[context, "Vdd, nPrechargeB1, nPrechargeB2, Bit, nBit"],
instances:
LIST [
[actual: "gate: nPrechargeB1, ch1: Bit, ch2: Vdd",
type: peTranType],
[actual: "gate: nPrechargeB2, ch1: nBit, ch2: Vdd",
type: peTranType]]];
IF GetBool[context, $PWCore] THEN PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
IF GetBool[context, $Sinix] THEN [] ← Sinix.ExtractObj[PWCore.GetLayout[cellType]];
IF GetBool[context, $Rosemary] THEN Rosemary.Bind[cellType: cellType, roseClassName: PrechargeSliceRoseClass];
CoreProperties.PutCellTypeProp[on: cellType, prop: CoreFlatten.CoreFlattenCutSets, value: LIST["JustAboveTransistors"]];
};
PrechargeSliceRoseClass: ROPE = Rosemary.Register[roseClassName: PrechargeSlice, init: PrechargeInit, evalSimple: PrechargeSimple];
Vdd: NAT = 0;
nPrechargeB1: NAT = 1;
nPrechargeB2: NAT = 2;
Bit: NAT = 3;
nBit: NAT = 4;
PrechargeInit: Rosemary.InitProc = {
FOR port:
NAT
IN [0..p.size)
DO
p[port].type ← b;
ENDLOOP;
};
PrechargeSimple: Rosemary.EvalProc = {
IF NOT p[Vdd].b THEN SIGNAL Rosemary.Stop[];
IF NOT p[nPrechargeB1].b=p[nPrechargeB2].b THEN SIGNAL Rosemary.Stop[];
p[nBit].d ← p[Bit].d ← IF NOT p[nPrechargeB1].b THEN drive ELSE none;
p[nBit].b ← p[Bit].b ← TRUE;
};
PrechargeStich:
ROPE = RegisterStructureProc[name: "PrechargeStich", proc: CreatePrechargeStitch];
CreatePrechargeStitch: StructureProc = {
cellType ← CreateRecordCell[
name: PrechargeStich,
context: context,
public: CreateWires[context, "Vdd, VddWell, nPrechargeB1, nPrechargeB2"]];
IF GetBool[context, $PWCore] THEN PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
IF GetBool[context, $Sinix] THEN [] ← Sinix.ExtractObj[PWCore.GetLayout[cellType]];
};
BottomRight:
ROPE = RegisterStructureProc[name: "BottomRight", proc: CreateBottomRight];
CreateBottomRight: StructureProc = {
cellType ← CreateRecordCell[
name: BottomRight,
context: context,
public: CreateWires[context, "Vdd"]];
IF GetBool[context, $PWCore] THEN PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
IF GetBool[context, $Sinix] THEN [] ← Sinix.ExtractObj[PWCore.GetLayout[cellType]];
};
END.