DIRECTORY CoreCreate; CrossRAMSSI: CEDAR DEFINITIONS = BEGIN OPEN CoreCreate; CreateInverter: PROC [design: Design, width: NAT _ 4, ratio: REAL _ 2.5] RETURNS [cell: CellType]; CreateTristateBuffer: PROC [design: Design, width: NAT _ 4, ratio: REAL _ 2.5] RETURNS [cell: CellType]; CreateNAnd: PROC [design: Design, inputCount: NAT _ 2, width: NAT _ 4, ratio: REAL _ 2.5] RETURNS [cell: CellType]; CreateAnd: PROC [design: Design, inputCount: NAT _ 2, width: NAT _ 4, ratio: REAL _ 2.5] RETURNS [cell: CellType]; CreateNOr: PROC [design: Design, inputCount: NAT _ 2, width: NAT _ 4, ratio: REAL _ 2.5] RETURNS [cell: CellType]; CreateOr: PROC [design: Design, inputCount: NAT _ 2, width: NAT _ 4, ratio: REAL _ 2.5] RETURNS [cell: CellType]; NAndArgsRef: TYPE = REF NAndArgsRec; NAndArgsRec: TYPE = RECORD[inputCount: NAT _ 2]; END. ζCrossRAMSSI.mesa Copyright c 1985 by Xerox Corporation. All rights reversed. Last Edited by: Barth, August 3, 1985 11:09:13 am PDT Width refers to the effective N channel width. As transistors are stacked the actual width is increased accordingly. Ratio refers to the amount by which the effective N channel width is multiplied to compute the effective P channel width. The effective P channel width is rounded up to the nearest integer lambda. Ports: Vdd, Gnd, Input, Output Ports: Vdd, Gnd, nInput, Drive, nDrive, Output Ports: Vdd, Gnd, Input[0..inputCount), nOutput Ports: Vdd, Gnd, Input[0..inputCount), Output Ports: Vdd, Gnd, Input[0..inputCount), nOutput Ports: Vdd, Gnd, Input[0..inputCount), Output Behavioural Types Κ’˜J– "Cedar" stylešœ™Jšœ Οmœ1™