DIRECTORY CoreCreate, CoreTransistor, CrossRAMRAM, IO; CrossRAMRAMImpl: CEDAR PROGRAM IMPORTS CoreCreate, CoreTransistor, IO EXPORTS CrossRAMRAM = BEGIN OPEN CoreCreate, CrossRAMRAM; CreateRAM: PUBLIC PROC [design: Design, columnOcts, rowQuads: NAT] RETURNS [cell: CellType] = { name: ROPE _ "RAMArray"; IF (cell _ FetchCell[design, name])=NIL THEN { MakeSubArray: PROC [name: ROPE, static: BOOL] RETURNS [cell: CellType] = { cell _ CreateSequenceCell[design: design, name: name, baseCell: CreateRAMRow[design: design, columnOcts: columnOcts, static: static], count: rowQuads, sequencePorts: LIST["Word"], attribute: [$GenLayout, LIST[ $ArrayY]]]; }; static, dynamic: CellInstance; cell _ CreateRecordCell[design: design, name: name]; [] _ CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd"]]; [] _ CreatePublicWire[design: design, on: cell, name: "Word", type: CreateWireSequenceType[design: design, count: 4*rowQuads]]; [] _ CreatePublicWire[design: design, on: cell, names: LIST["Bit", "nBit"], type: CreateWireSequenceType[design: design, count: 8*columnOcts]]; static _ CreateCellInstance[design: design, in: cell, type: MakeSubArray["SRAMArray", TRUE], bind: IO.PutFR["Word: Word[0..%g)", IO.int[2*rowQuads]]]; dynamic _ CreateCellInstance[design: design, in: cell, type: MakeSubArray["DRAMArray", FALSE], bind: IO.PutFR["Word: Word[%g..%g)", IO.int[2*rowQuads], IO.int[4*rowQuads]]]; PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, LIST[ $AbutY, static, dynamic]]]; }; }; CreateRAMRow: PROC [design: Design, columnOcts: NAT, static: BOOL _ TRUE] RETURNS [cell: CellType] = { name: ROPE _ IO.PutFR["%g*%g", IF static THEN IO.rope["SRamRow"] ELSE IO.rope["DRamRow"], IO.int[columnOcts]]; IF (cell _ FetchCell[design, name])=NIL THEN { cell _ CreateSequenceCell[design: design, name: name, baseCell: CreateRAMOctStitch[design: design, static: static], count: columnOcts, sequencePorts: LIST["Bit", "nBit"], attribute: [$GenLayout, LIST[ $ArrayX]]]; }; }; CreateRAMOctStitch: PROC [design: Design, static: BOOL _ TRUE] RETURNS [cell: CellType] = { name: ROPE _ IF static THEN "SRamOctStitch" ELSE "DRamOctStitch"; IF (cell _ FetchCell[design, name])=NIL THEN { octet, stitch: CellInstance; cell _ CreateRecordCell[design: design, name: name]; IF static THEN [] _ CreatePublicWire[design: design, on: cell, name: "Vdd"]; [] _ CreatePublicWire[design: design, on: cell, name: "Gnd"]; [] _ CreatePublicWire[design: design, on: cell, name: "Word", type: CreateWireSequenceType[design: design, count: 2]]; [] _ CreatePublicWire[design: design, on: cell, names: LIST["Bit", "nBit"], type: CreateWireSequenceType[design: design, count: 8]]; octet _ CreateCellInstance[design: design, in: cell, type: CreateRAMOct[design: design, static: static]]; stitch _ CreateCellInstance[design: design, in: cell, type: CreateRAMStitch[design: design, static: static]]; PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, LIST[ $AbutX, octet, stitch]]]; }; }; CreateRAMOct: PROC [design: Design, static: BOOL _ TRUE] RETURNS [cell: CellType] = { name: ROPE _ IF static THEN "SRamOct" ELSE "DRamOct"; IF (cell _ FetchCell[design, name])=NIL THEN { cell _ CreateSequenceCell[design: design, name: name, baseCell: CreateTwoRAMBits[design: design, static: static], count: 8, sequencePorts: LIST["Bit", "nBit"], attribute: [$GenLayout, LIST[ $ArrayX]]]; }; }; CreateTwoRAMBits: PROC [design: Design, static: BOOL _ TRUE] RETURNS [cell: CellType] = { name: ROPE _ IF static THEN "SRamTwoBits" ELSE "DRamTwoBits"; IF (cell _ FetchCell[design, name])=NIL THEN { cell _ CreateSequenceCell[design: design, name: name, baseCell: CreateRAMBit[design: design, static: static], count: 2, sequencePorts: LIST["Word"], attribute: [$GenLayout, LIST[ $Get]]]; }; }; CreateRAMBit: PROC [design: Design, static: BOOL _ TRUE] RETURNS [cell: CellType] = { name: ROPE _ IF static THEN "SRAMBit" ELSE "DRAMBit"; IF (cell _ FetchCell[design, name])=NIL THEN { n: CellType _ CoreTransistor.Create[args: NEW[CoreTransistor.TransistorRec _ [type: nE]]]; cell _ CreateRecordCell[design: design, name: name]; [] _ CreatePublicWire[design: design, on: cell, names: LIST["Gnd", "Word", "Bit", "nBit"]]; [] _ CreateWire[design: design, in: cell, names: LIST["State", "nState"]]; [] _ CreateCellInstance[design: design, in: cell, type: n, bindings: LIST["gate: Word, ch1: Bit, ch2: State", "gate: Word, ch1: nBit, ch2: nState", "gate: nState, ch1: State, ch2: Gnd", "gate: State, ch1: nState, ch2: Gnd"]]; IF static THEN { p: CellType _ CoreTransistor.Create[args: NEW[CoreTransistor.TransistorRec _ [type: pE]]]; [] _ CreatePublicWire[design: design, on: cell, name: "Vdd"]; [] _ CreateCellInstance[design: design, in: cell, type: p, bindings: LIST["gate: State, ch1: Vdd, ch2: nState", "gate: nState, ch1: Vdd, ch2: State"]]; }; }; }; CreateRAMStitch: PROC [design: Design, static: BOOL _ TRUE] RETURNS [cell: CellType] = { name: ROPE _ IF static THEN "SRamStitch" ELSE "DRamStitch"; IF (cell _ FetchCell[design, name])=NIL THEN { cell _ CreateRecordCell[design: design, name: name, attribute: [$GenLayout, LIST[ $Get]]]; [] _ CreatePublicWire[design: design, on: cell, name: "Gnd"]; [] _ CreatePublicWire[design: design, on: cell, name: "Word", type: CreateWireSequenceType[design: design, count: 2]]; IF static THEN [] _ CreatePublicWire[design: design, on: cell, name: "Vdd"]; }; }; END. πCrossRAMRAMImpl.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Barth, September 26, 1985 1:56:35 pm PDT Ports: Gnd, Word[0..2), Bit[0..8*columnOcts), nBit[0..8*columnOcts), IF static THEN Vdd Ports: Gnd, Word[0..2), Bit[0..8), nBit[0..8), IF static THEN Vdd Ports: Gnd, Word[0..2), Bit[0..8), nBit[0..8), IF static THEN Vdd Ports: Gnd, Word[0..2), Bit, nBit, IF static THEN Vdd Ports: Gnd, Word, Bit, nBit, IF static THEN Vdd Ports: Gnd, Word[0..2), IF static THEN Vdd ΚΫ– "cedar" style˜codešœ™Kšœ Οmœ1™˜LKšœ=˜=Kšœv˜vKšœ7žœI˜„Kšœi˜iKšœm˜mJšœEžœ˜dK˜—Kšœ˜K˜—Jšœ/žœžœ™Aš Ÿ œžœžœžœžœ˜UJš œžœžœžœ žœ ˜5šžœ"žœžœ˜.Kšœ‹žœ)žœ ˜ΙK˜—Kšœ˜K˜—Jšœ#žœžœ™5š Ÿœžœžœžœžœ˜YJš œžœžœžœžœ˜=šžœ"žœžœ˜.Kšœ‡žœ"žœ ˜»K˜—Kšœ˜K˜—Jšœžœžœ™/š Ÿ œžœžœžœžœ˜UJš œžœžœžœ žœ ˜5šžœ"žœžœ˜.Kšœ*žœ-˜ZKšœ4˜4Kšœ7žœ ˜[Kšœ1žœ˜JKšœEžœ˜˜αšžœžœ˜Kšœ*žœ-˜ZKšœ=˜=KšœEžœN˜—K˜—K˜—Kšœ˜K˜—Jšœžœžœ™*š Ÿœžœžœžœžœ˜XJš œžœžœžœžœ˜;šžœ"žœžœ˜.KšœLžœ ˜ZKšœ=˜=Kšœv˜vKšžœžœ>˜LK˜—Kšœ˜K˜—Kšžœ˜K˜—…—"ν