CrossRAMTopImpl.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Barth, September 26, 1985 2:17:26 pm PDT
Louis Monier September 20, 1985 6:19:42 pm PDT
DIRECTORY BitOps, CoreCreate, CrossRAMDataBuffer, CrossRAMSSI, CrossRAMTop, IO, Rope;
CrossRAMTopImpl: CEDAR PROGRAM
IMPORTS BitOps, CoreCreate, CrossRAMDataBuffer, CrossRAMSSI, IO, Rope
EXPORTS CrossRAMTop =
BEGIN OPEN CoreCreate, CrossRAMTop;
CreateTop: PUBLIC PROC [design: Design, addressBits, addressDecoderBits, columnOcts, select, log2Select: NAT] RETURNS [cell: CellType] = {
name: ROPE ← "CrossRAMTop";
IF (cell ← FetchCell[design, name])=NIL THEN {
decoderLeft, decoderDriver, decoderLogicDriver, dataBuffer, dataBufferRight: CellInstance;
cell ← CreateRecordCell[design: design, name: name];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd", "WriteB", "nWriteB", "ReadB", "nReadB"]];
[] ← CreatePublicWire[design: design, on: cell, name: "AddressB", type: CreateWireSequenceType[design: design, count: addressBits]];
[] ← CreatePublicWire[design: design, on: cell, name: "DataB", type: CreateWireSequenceType[design: design, count: columnOcts]];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["AdrBit", "nAdrBit"], type: CreateWireSequenceType[design: design, count: addressDecoderBits]];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Bit", "nBit"], type: CreateWireSequenceType[design: design, count: select*columnOcts]];
[] ← CreateWire[design: design, in: cell, name: "Select", type: CreateWireSequenceType[design: design, count: select]];
decoderLeft ← CreateCellInstance[design: design, in: cell, type: CreateDecoderDriverLeft[design: design, log2Select: log2Select], bind: IO.PutFR["AddressB: AddressB[0..%g)", IO.int[log2Select]]];
decoderDriver ← CreateCellInstance[design: design, in: cell, type: CreateDecoderDriverSequence[design: design, driverPairCount: (addressBits-log2Select)/2, log2Select: log2Select], bind: IO.PutFR["LowAddressB: AddressB[0..%g), HighAddressB: AddressB[%g..%g)", IO.int[log2Select], IO.int[log2Select], IO.int[addressBits]]];
decoderLogicDriver ← CreateCellInstance[design: design, in: cell, type: CreateDecoderLogicDriver[design: design, select: select, log2Select: log2Select], bind: IO.PutFR["AddressB: AddressB[0..%g), AdrBit: AdrBit[%g], nAdrBit: nAdrBit[%g]", IO.int[log2Select], IO.int[addressDecoderBits-1], IO.int[addressDecoderBits-1]]];
dataBuffer ← CreateCellInstance[design: design, in: cell, type: CrossRAMDataBuffer.CreateDataBuffer[design: design, select: select, columnOcts: columnOcts]];
dataBufferRight ← CreateCellInstance[design: design, in: cell, type: CreateDataBufferRight[design: design]];
PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, LIST[ $AbutX, decoderLeft, decoderDriver, decoderLogicDriver, dataBuffer, dataBufferRight]]];
};
};
Ports: Vdd, AddressB[0..log2Select)
CreateDecoderDriverLeft: PROC [design: Design, log2Select: NAT] RETURNS [cell: CellType] = {
name: ROPE ← "DecoderDriverLeft";
IF (cell ← FetchCell[design, name])=NIL THEN {
cell ← CreateRecordCell[design: design, name: name, attribute: [$GenLayout, $Get]];
[] ← CreatePublicWire[design: design, on: cell, name: "Vdd"];
[] ← CreatePublicWire[design: design, on: cell, name: "AddressB", type: CreateWireSequenceType[design: design, count: log2Select]];
};
};
Ports: Vdd, Gnd, LowAddressB[0..log2Select), HighAddressB[0..2*driverPairCount), AdrBit[0..2*driverPairCount), nAdrBit[0..2*driverPairCount)
CreateDecoderDriverSequence: PROC [design: Design, driverPairCount, log2Select: NAT] RETURNS [cell: CellType] = {
name: ROPE ← "DecoderDriverSequence";
IF (cell ← FetchCell[design, name])=NIL THEN {
driverCount: NAT ← 2*driverPairCount;
MakeStackRope: PROC [base: ROPE] RETURNS [ROPE] = {
RETURN[IO.PutFR["%g: %g[0..%g)", IO.rope[base], IO.rope[base], IO.int[driverCount-2]]];
};
MakePairRope: PROC [base: ROPE] RETURNS [ROPE] = {
RETURN[IO.PutFR["%g: %g[%g..%g)", IO.rope[base], IO.rope[base], IO.int[driverCount-2], IO.int[driverCount]]];
};
stack, tree: CellInstance;
decoderDriver: CellType ← CreateDecoderDriver[design: design, log2Select: log2Select];
stackDriver: CellType ← CreateSequenceCell[design: design, name: "DecoderDriverStackBitSeq", baseCell: CreateIdentityCell[design: design, name: "DecoderDriverStackBit", baseCell: decoderDriver, attribute: [$GenLayout, LIST[$Inst, decoderDriver, "RemoveForStackDecoderBit"]]], count: driverPairCount-1, sequencePorts: LIST["HighAddressB", "AdrBit", "nAdrBit"], attribute: [$GenLayout, $ArrayX]];
treeDriver: CellType ← CreateIdentityCell[design: design, name: "DecoderDriverTreeBit", baseCell: decoderDriver, attribute: [$GenLayout, LIST[ $Inst, decoderDriver, "RemoveForTreeDecoderBit"]]];
cell ← CreateRecordCell[design: design, name: name];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd"]];
[] ← CreatePublicWire[design: design, on: cell, name: "LowAddressB", type: CreateWireSequenceType[design: design, count: log2Select]];
[] ← CreatePublicWire[design: design, on: cell, name: "HighAddressB", type: CreateWireSequenceType[design: design, count: driverCount]];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["AdrBit", "nAdrBit"], type: CreateWireSequenceType[design: design, count: driverCount]];
stack ← CreateCellInstance[design: design, in: cell, type: stackDriver, bind: Rope.Cat[MakeStackRope["HighAddressB"], ", ", MakeStackRope["AdrBit"], ", ", MakeStackRope["nAdrBit"]]];
tree ← CreateCellInstance[design: design, in: cell, type: treeDriver, bind: Rope.Cat[MakePairRope["HighAddressB"], ", ", MakePairRope["AdrBit"], ", ", MakePairRope["nAdrBit"]]];
PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, LIST[ $AbutX, stack, tree]]];
};
};
Ports: Vdd, Gnd, LowAddressB[0..log2Select), HighAddressB[0..2), AdrBit[0..2), nAdrBit[0..2),
CreateDecoderDriver: PROC [design: Design, log2Select: NAT] RETURNS [cell: CellType] = {
name: ROPE ← "DecoderDriver";
cell ← CreateSequenceCell[design: design, name: name, baseCell: CreateDecoderDriverHalf[design: design, log2Select: log2Select], count: 2, sequencePorts: LIST["HighAddressB", "AdrBit", "nAdrBit"], attribute: [$GenLayout, $Get]];
};
Ports: Vdd, Gnd, LowAddressB[0..log2Select), HighAddressB, AdrBit, nAdrBit
CreateDecoderDriverHalf: PROC [design: Design, log2Select: NAT] RETURNS [cell: CellType] = {
name: ROPE ← "DecoderDriverHalf";
IF (cell ← FetchCell[design, name])=NIL THEN {
invert16: CellType ← CrossRAMSSI.CreateInverter[design: design, width: 16];
cell ← CreateRecordCell[design: design, name: name];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd", "HighAddressB", "AdrBit", "nAdrBit"]];
[] ← CreatePublicWire[design: design, on: cell, name: "LowAddressB", type: CreateWireSequenceType[design: design, count: log2Select]];
[] ← CreateWire[design: design, in: cell, name: "nAddress"];
[] ← CreateCellInstance[design: design, in: cell, type: CrossRAMSSI.CreateInverter[design: design, width: 4], bind: "Input: HighAddressB, Output: nAddress"];
[] ← CreateCellInstance[design: design, in: cell, type: invert16, bind: "Input: nAddress, Output: AdrBit"];
[] ← CreateCellInstance[design: design, in: cell, type: invert16, bind: "Input: HighAddressB, Output: nAdrBit"];
};
};
Ports: Vdd, Gnd, AddressB[0..log2Select), AdrBit, nAdrBit, Select[0..select)
CreateDecoderLogicDriver: PROC [design: Design, select, log2Select: NAT] RETURNS [cell: CellType] = {
name: ROPE ← "DecoderLogicDriver";
IF (cell ← FetchCell[design, name])=NIL THEN {
invert8: CellType ← CrossRAMSSI.CreateInverter[design: design, width: 8];
and: CellType ← CrossRAMSSI.CreateAnd[design: design, inputCount: log2Select, width: 16];
cell ← CreateRecordCell[design: design, name: name, attribute: [$GenLayout, $Get]];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd", "AdrBit", "nAdrBit"]];
[] ← CreatePublicWire[design: design, on: cell, name: "AddressB", type: CreateWireSequenceType[design: design, count: log2Select]];
[] ← CreatePublicWire[design: design, on: cell, name: "Select", type: CreateWireSequenceType[design: design, count: select]];
[] ← CreateWire[design: design, in: cell, name: "nHighAddressB", type: CreateWireSequenceType[design: design, count: log2Select]];
FOR adrBit: NAT IN [0..log2Select) DO
[] ← CreateCellInstance[design: design, in: cell, type: invert8, bind: IO.PutFR["Input: AddressB[%g], Output: nHighAddressB[%g]", IO.int[adrBit], IO.int[adrBit]]];
ENDLOOP;
FOR select: NAT IN [0..select) DO
bind: ROPE ← NIL;
FOR adrBit: NAT IN [0..log2Select) DO
bind ← Rope.Cat[bind, IF BitOps.EBFW[select, log2Select, adrBit] THEN IO.PutFR["AddressB[%g]", IO.int[adrBit]] ELSE IO.PutFR["nHighAddressB[%g]", IO.int[adrBit]]];
IF adrBit < log2Select-1 THEN bind ← Rope.Cat[bind, ", "];
ENDLOOP;
[] ← CreateCellInstance[design: design, in: cell, type: and, bind: IO.PutFR["Input: [%g], Output: Select[%g]", IO.rope[bind], IO.int[select]]];
ENDLOOP;
};
};
Ports: Vdd, WriteB, nWriteB, ReadB, nReadB
CreateDataBufferRight: PROC [design: Design] RETURNS [cell: CellType] = {
name: ROPE ← "DataBufferRight";
IF (cell ← FetchCell[design, name])=NIL THEN {
cell ← CreateRecordCell[design: design, name: name, attribute: [$GenLayout, $Get]];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "WriteB", "nWriteB", "ReadB", "nReadB"]];
};
};
END.