CrossRAMRAMImpl.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Barth, September 26, 1985 1:56:35 pm PDT
DIRECTORY CoreCreate, CoreTransistor, CrossRAMRAM, IO;
CrossRAMRAMImpl:
CEDAR
PROGRAM
IMPORTS CoreCreate, CoreTransistor, IO
EXPORTS CrossRAMRAM =
BEGIN OPEN CoreCreate, CrossRAMRAM;
CreateRAM:
PUBLIC
PROC [design: Design, columnOcts, rowQuads:
NAT]
RETURNS [cell: CellType] = {
name: ROPE ← "RAMArray";
IF (cell ← FetchCell[design, name])=
NIL
THEN {
MakeSubArray:
PROC [name:
ROPE, static:
BOOL]
RETURNS [cell: CellType] = {
cell ← CreateSequenceCell[design: design, name: name, baseCell: CreateRAMRow[design: design, columnOcts: columnOcts, static: static], count: rowQuads, sequencePorts: LIST["Word"], attribute: [$GenLayout, LIST[ $ArrayY]]];
};
static, dynamic: CellInstance;
cell ← CreateRecordCell[design: design, name: name];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd"]];
[] ← CreatePublicWire[design: design, on: cell, name: "Word", type: CreateWireSequenceType[design: design, count: 4*rowQuads]];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Bit", "nBit"], type: CreateWireSequenceType[design: design, count: 8*columnOcts]];
static ← CreateCellInstance[design: design, in: cell, type: MakeSubArray["SRAMArray", TRUE], bind: IO.PutFR["Word: Word[0..%g)", IO.int[2*rowQuads]]];
dynamic ← CreateCellInstance[design: design, in: cell, type: MakeSubArray["DRAMArray", FALSE], bind: IO.PutFR["Word: Word[%g..%g)", IO.int[2*rowQuads], IO.int[4*rowQuads]]];
PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, LIST[ $AbutY, static, dynamic]]];
};
};
Ports: Gnd, Word[0..2), Bit[0..8*columnOcts), nBit[0..8*columnOcts), IF static THEN Vdd
CreateRAMRow:
PROC [design: Design, columnOcts:
NAT, static:
BOOL ←
TRUE]
RETURNS [cell: CellType] = {
name: ROPE ← IO.PutFR["%g*%g", IF static THEN IO.rope["SRamRow"] ELSE IO.rope["DRamRow"], IO.int[columnOcts]];
IF (cell ← FetchCell[design, name])=
NIL
THEN {
cell ← CreateSequenceCell[design: design, name: name, baseCell: CreateRAMOctStitch[design: design, static: static], count: columnOcts, sequencePorts: LIST["Bit", "nBit"], attribute: [$GenLayout, LIST[ $ArrayX]]];
};
};
Ports: Gnd, Word[0..2), Bit[0..8), nBit[0..8), IF static THEN Vdd
CreateRAMOctStitch:
PROC [design: Design, static:
BOOL ←
TRUE]
RETURNS [cell: CellType] = {
name: ROPE ← IF static THEN "SRamOctStitch" ELSE "DRamOctStitch";
IF (cell ← FetchCell[design, name])=
NIL
THEN {
octet, stitch: CellInstance;
cell ← CreateRecordCell[design: design, name: name];
IF static THEN [] ← CreatePublicWire[design: design, on: cell, name: "Vdd"];
[] ← CreatePublicWire[design: design, on: cell, name: "Gnd"];
[] ← CreatePublicWire[design: design, on: cell, name: "Word", type: CreateWireSequenceType[design: design, count: 2]];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Bit", "nBit"], type: CreateWireSequenceType[design: design, count: 8]];
octet ← CreateCellInstance[design: design, in: cell, type: CreateRAMOct[design: design, static: static]];
stitch ← CreateCellInstance[design: design, in: cell, type: CreateRAMStitch[design: design, static: static]];
PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, LIST[ $AbutX, octet, stitch]]];
};
};
Ports: Gnd, Word[0..2), Bit[0..8), nBit[0..8), IF static THEN Vdd
CreateRAMOct:
PROC [design: Design, static:
BOOL ←
TRUE]
RETURNS [cell: CellType] = {
name: ROPE ← IF static THEN "SRamOct" ELSE "DRamOct";
IF (cell ← FetchCell[design, name])=
NIL
THEN {
cell ← CreateSequenceCell[design: design, name: name, baseCell: CreateTwoRAMBits[design: design, static: static], count: 8, sequencePorts: LIST["Bit", "nBit"], attribute: [$GenLayout, LIST[ $ArrayX]]];
};
};
Ports: Gnd, Word[0..2), Bit, nBit, IF static THEN Vdd
CreateTwoRAMBits:
PROC [design: Design, static:
BOOL ←
TRUE]
RETURNS [cell: CellType] = {
name: ROPE ← IF static THEN "SRamTwoBits" ELSE "DRamTwoBits";
IF (cell ← FetchCell[design, name])=
NIL
THEN {
cell ← CreateSequenceCell[design: design, name: name, baseCell: CreateRAMBit[design: design, static: static], count: 2, sequencePorts: LIST["Word"], attribute: [$GenLayout, LIST[ $Get]]];
};
};
Ports: Gnd, Word, Bit, nBit, IF static THEN Vdd
CreateRAMBit:
PROC [design: Design, static:
BOOL ←
TRUE]
RETURNS [cell: CellType] = {
name: ROPE ← IF static THEN "SRAMBit" ELSE "DRAMBit";
IF (cell ← FetchCell[design, name])=
NIL
THEN {
n: CellType ← CoreTransistor.Create[args: NEW[CoreTransistor.TransistorRec ← [type: nE]]];
cell ← CreateRecordCell[design: design, name: name];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Gnd", "Word", "Bit", "nBit"]];
[] ← CreateWire[design: design, in: cell, names: LIST["State", "nState"]];
[] ← CreateCellInstance[design: design, in: cell, type: n, bindings: LIST["gate: Word, ch1: Bit, ch2: State", "gate: Word, ch1: nBit, ch2: nState", "gate: nState, ch1: State, ch2: Gnd", "gate: State, ch1: nState, ch2: Gnd"]];
IF static
THEN {
p: CellType ← CoreTransistor.Create[args: NEW[CoreTransistor.TransistorRec ← [type: pE]]];
[] ← CreatePublicWire[design: design, on: cell, name: "Vdd"];
[] ← CreateCellInstance[design: design, in: cell, type: p, bindings: LIST["gate: State, ch1: Vdd, ch2: nState", "gate: nState, ch1: Vdd, ch2: State"]];
};
};
};
Ports: Gnd, Word[0..2), IF static THEN Vdd
CreateRAMStitch:
PROC [design: Design, static:
BOOL ←
TRUE]
RETURNS [cell: CellType] = {
name: ROPE ← IF static THEN "SRamStitch" ELSE "DRamStitch";
IF (cell ← FetchCell[design, name])=
NIL
THEN {
cell ← CreateRecordCell[design: design, name: name, attribute: [$GenLayout, LIST[ $Get]]];
[] ← CreatePublicWire[design: design, on: cell, name: "Gnd"];
[] ← CreatePublicWire[design: design, on: cell, name: "Word", type: CreateWireSequenceType[design: design, count: 2]];
IF static THEN [] ← CreatePublicWire[design: design, on: cell, name: "Vdd"];
};
};
END.