<> <> <> <<>> DIRECTORY CoreCreate, CrossRAMPads, CrossRAMSSI, CoreTransistor; CrossRAMPadsImpl: CEDAR PROGRAM IMPORTS CrossRAMSSI, CoreCreate, CoreTransistor EXPORTS CrossRAMPads = BEGIN OPEN CoreCreate; CreateBasicInputPad: PUBLIC PROC [design: Design] RETURNS [ct: CellType] = { name: ROPE _ "BasicInputPad"; IF (ct _ FetchCell[design, name])=NIL THEN { invert: CellType _ CrossRAMSSI.CreateInverter[design: design, width: 64, ratio: 0.125]; ct _ CreateRecordCell[design: design, name: name]; [] _ CreatePublicWire[design: design, on: ct, name: "Vdd"]; [] _ CreatePublicWire[design: design, on: ct, name: "Gnd"]; [] _ CreatePublicWire[design: design, on: ct, name: "Pad"]; [] _ CreatePublicWire[design: design, on: ct, name: "nOutput"]; [] _ CreateCellInstance[design: design, in: ct, type: invert, bind: "Input: Pad, Output: nOutput"]; }; }; CreateInputPad: PUBLIC PROC [design: Design] RETURNS [ct: CellType] = { name: ROPE _ "InputPad"; IF (ct _ FetchCell[design, name])=NIL THEN { bp: CellType _ CreateBasicInputPad[design: design]; invert: CellType _ CrossRAMSSI.CreateInverter[design: design, width: 8]; ct _ CreateRecordCell[design: design, name: name]; [] _ CreatePublicWire[design: design, on: ct, name: "Vdd"]; [] _ CreatePublicWire[design: design, on: ct, name: "Gnd"]; [] _ CreatePublicWire[design: design, on: ct, name: "Pad"]; [] _ CreatePublicWire[design: design, on: ct, name: "Output"]; [] _ CreateWire[design: design, in: ct, name: "nOutput"]; [] _ CreateCellInstance[design: design, in: ct, type: bp]; [] _ CreateCellInstance[design: design, in: ct, type: invert, bind: "Input: nOutput, Output: Output"]; }; }; CreateDifferentialInputPad: PUBLIC PROC [design: Design] RETURNS [ct: CellType] = { name: ROPE _ "DifferentialInputPad"; IF (ct _ FetchCell[design, name])=NIL THEN { bp: CellType _ CreateBasicInputPad[design: design]; invert8: CellType _ CrossRAMSSI.CreateInverter[design: design, width: 8]; invert4: CellType _ CrossRAMSSI.CreateInverter[design: design, width: 4]; ct _ CreateRecordCell[design: design, name: name]; [] _ CreatePublicWire[design: design, on: ct, name: "Vdd"]; [] _ CreatePublicWire[design: design, on: ct, name: "Gnd"]; [] _ CreatePublicWire[design: design, on: ct, name: "Pad"]; [] _ CreatePublicWire[design: design, on: ct, name: "Output"]; [] _ CreatePublicWire[design: design, on: ct, name: "nOutput"]; [] _ CreateWire[design: design, in: ct, name: "nbpOut"]; [] _ CreateWire[design: design, in: ct, name: "bpOut"]; [] _ CreateCellInstance[design: design, in: ct, type: bp, bind: "nOutput: nbpOut"]; [] _ CreateCellInstance[design: design, in: ct, type: invert8, bind: "Input: nbpOut, Output: Output"]; [] _ CreateCellInstance[design: design, in: ct, type: invert4, bind: "Input: nbpOut, Output: bpOut"]; [] _ CreateCellInstance[design: design, in: ct, type: invert8, bind: "Input: bpOut, Output: nOutput"]; }; }; CreateBidirectionalPad: PUBLIC PROC [design: Design] RETURNS [ct: CellType] = { name: ROPE _ "BidirectionalPad"; IF (ct _ FetchCell[design, name])=NIL THEN { bp: CellType _ CreateBasicInputPad[design: design]; tristate: CellType _ CrossRAMSSI.CreateTristateBuffer[design: design, width: 32]; nand2: CellType _ CrossRAMSSI.CreateNAnd[design: design, width: 8]; nor2: CellType _ CrossRAMSSI.CreateNOr[design: design, width: 8]; p: CellType _ CoreTransistor.Create[args: NEW[ CoreTransistor.TransistorRec _ [type: pE, width: 600]]]; n: CellType _ CoreTransistor.Create[args: NEW[ CoreTransistor.TransistorRec _ [type: nE, width: 300]]]; ct _ CreateRecordCell[design: design, name: name]; [] _ CreatePublicWire[design: design, on: ct, name: "Vdd"]; [] _ CreatePublicWire[design: design, on: ct, name: "Gnd"]; [] _ CreatePublicWire[design: design, on: ct, name: "Read"]; [] _ CreatePublicWire[design: design, on: ct, name: "nRead"]; [] _ CreatePublicWire[design: design, on: ct, name: "Write"]; [] _ CreatePublicWire[design: design, on: ct, name: "nWrite"]; [] _ CreatePublicWire[design: design, on: ct, name: "Pad"]; [] _ CreatePublicWire[design: design, on: ct, name: "Data"]; [] _ CreateWire[design: design, in: ct, name: "nandOut"]; [] _ CreateWire[design: design, in: ct, name: "norOut"]; [] _ CreateWire[design: design, in: ct, name: "nbpOut"]; [] _ CreateCellInstance[design: design, in: ct, type: bp, bind: "nOutput: nbpOut"]; [] _ CreateCellInstance[design: design, in: ct, type: tristate, bind: "nInput: nbpOut, Drive: Write, nDrive: nWrite, Output: Data"]; [] _ CreateCellInstance[design: design, in: ct, type: nand2, bind: "Input: [Read, Data], nOutput: nandOut"]; [] _ CreateCellInstance[design: design, in: ct, type: nor2, bind: "Input: [nRead, Data], nOutput: norOut"]; [] _ CreateCellInstance[design: design, in: ct, type: p, bind: "gate: nandOut, ch1: Vdd, ch2: Pad"]; [] _ CreateCellInstance[design: design, in: ct, type: n, bind: "gate: norOut, ch1: Pad, ch2: Gnd"]; }; }; END.