CrossRAMPadsImpl.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Last Edited by: Barth, September 4, 1985 2:15:25 pm PDT
DIRECTORY CoreCreate, CrossRAMPads, CrossRAMSSI, CoreTransistor;
CrossRAMPadsImpl: CEDAR PROGRAM
IMPORTS CrossRAMSSI, CoreCreate, CoreTransistor
EXPORTS CrossRAMPads =
BEGIN OPEN CoreCreate;
CreateBasicInputPad: PUBLIC PROC [design: Design] RETURNS [ct: CellType] = {
name: ROPE ← "BasicInputPad";
IF (ct ← FetchCell[design, name])=NIL THEN {
invert: CellType ← CrossRAMSSI.CreateInverter[design: design, width: 64, ratio: 0.125];
ct ← CreateRecordCell[design: design, name: name];
[] ← CreatePublicWire[design: design, on: ct, name: "Vdd"];
[] ← CreatePublicWire[design: design, on: ct, name: "Gnd"];
[] ← CreatePublicWire[design: design, on: ct, name: "Pad"];
[] ← CreatePublicWire[design: design, on: ct, name: "nOutput"];
[] ← CreateCellInstance[design: design, in: ct, type: invert, bind: "Input: Pad, Output: nOutput"];
};
};
CreateInputPad: PUBLIC PROC [design: Design] RETURNS [ct: CellType] = {
name: ROPE ← "InputPad";
IF (ct ← FetchCell[design, name])=NIL THEN {
bp: CellType ← CreateBasicInputPad[design: design];
invert: CellType ← CrossRAMSSI.CreateInverter[design: design, width: 8];
ct ← CreateRecordCell[design: design, name: name];
[] ← CreatePublicWire[design: design, on: ct, name: "Vdd"];
[] ← CreatePublicWire[design: design, on: ct, name: "Gnd"];
[] ← CreatePublicWire[design: design, on: ct, name: "Pad"];
[] ← CreatePublicWire[design: design, on: ct, name: "Output"];
[] ← CreateWire[design: design, in: ct, name: "nOutput"];
[] ← CreateCellInstance[design: design, in: ct, type: bp];
[] ← CreateCellInstance[design: design, in: ct, type: invert, bind: "Input: nOutput, Output: Output"];
};
};
CreateDifferentialInputPad: PUBLIC PROC [design: Design] RETURNS [ct: CellType] = {
name: ROPE ← "DifferentialInputPad";
IF (ct ← FetchCell[design, name])=NIL THEN {
bp: CellType ← CreateBasicInputPad[design: design];
invert8: CellType ← CrossRAMSSI.CreateInverter[design: design, width: 8];
invert4: CellType ← CrossRAMSSI.CreateInverter[design: design, width: 4];
ct ← CreateRecordCell[design: design, name: name];
[] ← CreatePublicWire[design: design, on: ct, name: "Vdd"];
[] ← CreatePublicWire[design: design, on: ct, name: "Gnd"];
[] ← CreatePublicWire[design: design, on: ct, name: "Pad"];
[] ← CreatePublicWire[design: design, on: ct, name: "Output"];
[] ← CreatePublicWire[design: design, on: ct, name: "nOutput"];
[] ← CreateWire[design: design, in: ct, name: "nbpOut"];
[] ← CreateWire[design: design, in: ct, name: "bpOut"];
[] ← CreateCellInstance[design: design, in: ct, type: bp, bind: "nOutput: nbpOut"];
[] ← CreateCellInstance[design: design, in: ct, type: invert8, bind: "Input: nbpOut, Output: Output"];
[] ← CreateCellInstance[design: design, in: ct, type: invert4, bind: "Input: nbpOut, Output: bpOut"];
[] ← CreateCellInstance[design: design, in: ct, type: invert8, bind: "Input: bpOut, Output: nOutput"];
};
};
CreateBidirectionalPad: PUBLIC PROC [design: Design] RETURNS [ct: CellType] = {
name: ROPE ← "BidirectionalPad";
IF (ct ← FetchCell[design, name])=NIL THEN {
bp: CellType ← CreateBasicInputPad[design: design];
tristate: CellType ← CrossRAMSSI.CreateTristateBuffer[design: design, width: 32];
nand2: CellType ← CrossRAMSSI.CreateNAnd[design: design, width: 8];
nor2: CellType ← CrossRAMSSI.CreateNOr[design: design, width: 8];
p: CellType ← CoreTransistor.Create[args: NEW[ CoreTransistor.TransistorRec ← [type: pE, width: 600]]];
n: CellType ← CoreTransistor.Create[args: NEW[ CoreTransistor.TransistorRec ← [type: nE, width: 300]]];
ct ← CreateRecordCell[design: design, name: name];
[] ← CreatePublicWire[design: design, on: ct, name: "Vdd"];
[] ← CreatePublicWire[design: design, on: ct, name: "Gnd"];
[] ← CreatePublicWire[design: design, on: ct, name: "Read"];
[] ← CreatePublicWire[design: design, on: ct, name: "nRead"];
[] ← CreatePublicWire[design: design, on: ct, name: "Write"];
[] ← CreatePublicWire[design: design, on: ct, name: "nWrite"];
[] ← CreatePublicWire[design: design, on: ct, name: "Pad"];
[] ← CreatePublicWire[design: design, on: ct, name: "Data"];
[] ← CreateWire[design: design, in: ct, name: "nandOut"];
[] ← CreateWire[design: design, in: ct, name: "norOut"];
[] ← CreateWire[design: design, in: ct, name: "nbpOut"];
[] ← CreateCellInstance[design: design, in: ct, type: bp, bind: "nOutput: nbpOut"];
[] ← CreateCellInstance[design: design, in: ct, type: tristate, bind: "nInput: nbpOut, Drive: Write, nDrive: nWrite, Output: Data"];
[] ← CreateCellInstance[design: design, in: ct, type: nand2, bind: "Input: [Read, Data], nOutput: nandOut"];
[] ← CreateCellInstance[design: design, in: ct, type: nor2, bind: "Input: [nRead, Data], nOutput: norOut"];
[] ← CreateCellInstance[design: design, in: ct, type: p, bind: "gate: nandOut, ch1: Vdd, ch2: Pad"];
[] ← CreateCellInstance[design: design, in: ct, type: n, bind: "gate: norOut, ch1: Pad, ch2: Gnd"];
};
};
END.