CrossRAMImpl.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Barth, September 19, 1985 10:31:16 am PDT
Louis Monier September 20, 1985 3:46:52 pm PDT
DIRECTORY CoreCreate, CrossRAM, CrossRAMBottom, CrossRAMDecoder, CrossRAMPads, CrossRAMRAM, CrossRAMTop, IO;
CrossRAMImpl: CEDAR PROGRAM
IMPORTS CoreCreate, CrossRAMBottom, CrossRAMDecoder, CrossRAMPads, CrossRAMRAM, CrossRAMTop, IO
EXPORTS CrossRAM =
BEGIN OPEN CoreCreate, CrossRAM;
rowQuads: INT = 60;
columnOcts: INT = 15;
addressBits: INT = 11;
dataBits: INT = columnOcts;
select: INT = 8;
log2Select: INT = 3;
addressDecoderBits: INT = 8;
AddressIndex: TYPE = [0..addressBits);
DataIndex: TYPE = [0..dataBits);
CreateCrossRAM: PUBLIC PROC [design: Design] RETURNS [cell: CellType] = {
name: ROPE ← "CrossRAM";
IF (cell ← FetchCell[design, name])=NIL THEN {
inner, outer: CellInstance;
cell ← CreateRecordCell[design: design, name: name];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd", "PadVdd", "PadGnd", "nPrecharge", "Access", "Write", "Read"]];
[] ← CreatePublicWire[design: design, on: cell, name: "Address", type: CreateWireSequenceType[design: design, count: addressBits]];
[] ← CreatePublicWire[design: design, on: cell, name: "Data", type: CreateWireSequenceType[design: design, count: dataBits]];
[] ← CreateWire[design: design, in: cell, names: LIST["nPrechargeB", "AccessB", "WriteB", "nWriteB", "ReadB", "nReadB"]];
[] ← CreateWire[design: design, in: cell, name: "AddressB", type: CreateWireSequenceType[design: design, count: addressBits]];
[] ← CreateWire[design: design, in: cell, name: "DataB", type: CreateWireSequenceType[design: design, count: dataBits]];
inner ← CreateCellInstance[design: design, in: cell, type: CreateInner[design: design]];
outer ← CreateCellInstance[design: design, in: cell, type: CreateCrossRAMPadFrame[design: design]];
PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, LIST[$Onion, inner, outer, $Center]]];
};
};
Ports: Vdd, Gnd, PadVdd, PadGnd, nPrecharge, Access, Write, Read, Address[0..addressBits), Data[0..dataBits), nPrechargeB, AccessB, WriteB, nWriteB, ReadB, nReadB, AddressB[0..addressBits), DataB[0..dataBits)
CreateCrossRAMPadFrame: PROC [design: Design] RETURNS [cell: CellType] = {
name: ROPE ← "CrossRamPadFrame";
IF (cell ← FetchCell[design, name])=NIL THEN {
inputPad: CellType ← CrossRAMPads.CreateInputPad[design: design];
differentialInputPad: CellType ← CrossRAMPads.CreateDifferentialInputPad[design: design];
bidirectionalPad: CellType ← CrossRAMPads.CreateBidirectionalPad[design: design];
dataWire: Wire ← CreateWireSequenceType[design: design, count: dataBits];
addressWire: Wire ← CreateWireSequenceType[design: design, count: addressBits];
cell ← CreateRecordCell[design: design, name: name, attribute: [$GenLayout, $Get]];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd", "PadVdd", "PadGnd", "nPrecharge", "Access", "Write", "Read"]];
[] ← CreatePublicWire[design: design, on: cell, name: "Address", type: addressWire];
[] ← CreatePublicWire[design: design, on: cell, name: "Data", type: dataWire];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["nPrechargeB", "AccessB", "WriteB", "nWriteB", "ReadB", "nReadB"]];
[] ← CreatePublicWire[design: design, on: cell, name: "AddressB", type: addressWire];
[] ← CreatePublicWire[design: design, on: cell, name: "DataB", type: dataWire];
[] ← CreateCellInstance[design: design, in: cell, type: inputPad, bind: "Vdd: PadVdd, Gnd: PadGnd, Pad: nPrecharge, Output: nPrechargeB"];
[] ← CreateCellInstance[design: design, in: cell, type: inputPad, bind: "Vdd: PadVdd, Gnd: PadGnd, Pad: Access, Output: AccessB"];
[] ← CreateCellInstance[design: design, in: cell, type: differentialInputPad, bind: "Vdd: PadVdd, Gnd: PadGnd, Pad: Write, Output: WriteB, nOutput: nWriteB"];
[] ← CreateCellInstance[design: design, in: cell, type: differentialInputPad, bind: "Vdd: PadVdd, Gnd: PadGnd, Pad: Read, Output: ReadB, nOutput: nReadB"];
FOR addressPad: AddressIndex IN AddressIndex DO
[] ← CreateCellInstance[design: design, in: cell, type: inputPad, bind: IO.PutFR["Vdd: PadVdd, Gnd: PadGnd, Pad: Address[%g], Output: AddressB[%g]", IO.int[addressPad], IO.int[addressPad]]];
ENDLOOP;
FOR dataPad: DataIndex IN DataIndex DO
[] ← CreateCellInstance[design: design, in: cell, type: bidirectionalPad, bind: IO.PutFR["Vdd: PadVdd, Gnd: PadGnd, Read: ReadB, nRead: ReadB, Write: WriteB, nWrite: nWriteB, Pad: Data[%g], Data: DataB[%g]", IO.int[dataPad], IO.int[dataPad]]];
ENDLOOP;
};
};
Ports: Vdd, Gnd, nPrechargeB, AccessB, WriteB, nWriteB, ReadB, nReadB, AddressB[0..addressBits), DataB[0..dataBits)
CreateInner: PUBLIC PROC [design: Design] RETURNS [cell: CellType] = {
name: ROPE ← "CrossRAMInner";
IF (cell ← FetchCell[design, name])=NIL THEN {
bottom, middle, top: CellInstance;
cell ← CreateRecordCell[design: design, name: name];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd", "nPrechargeB", "AccessB", "WriteB", "nWriteB", "ReadB", "nReadB"]];
[] ← CreatePublicWire[design: design, on: cell, name: "AddressB", type: CreateWireSequenceType[design: design, count: addressBits]];
[] ← CreatePublicWire[design: design, on: cell, name: "DataB", type: CreateWireSequenceType[design: design, count: dataBits]];
[] ← CreateWire[design: design, in: cell, names: LIST["AdrBit", "nAdrBit"], type: CreateWireSequenceType[design: design, count: addressDecoderBits]];
[] ← CreateWire[design: design, in: cell, names: LIST["Bit", "nBit"], type: CreateWireSequenceType[design: design, count: select*columnOcts]];
bottom ← CreateCellInstance[design: design, in: cell, type: CrossRAMBottom.CreateBottom[design: design, columnOcts: columnOcts, addressDecoderBits: addressDecoderBits-1]];
middle ← CreateCellInstance[design: design, in: cell, type: CreateMiddle[design: design]];
top ← CreateCellInstance[design: design, in: cell, type: CrossRAMTop.CreateTop[design: design, addressBits: addressBits, addressDecoderBits: addressDecoderBits, columnOcts: columnOcts, select: select, log2Select: log2Select]];
PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, LIST[$AbutY, bottom, middle, top]]];
};
};
Ports: Vdd, Gnd, AccessB, AdrBit[0..addressDecoderBits), nAdrBit[0..addressDecoderBits), Bit[0..select*columnOcts), nBit[0..select*columnOcts)
CreateMiddle: PROC [design: Design] RETURNS [cell: CellType] = {
name: ROPE ← "CrossRAMMiddle";
IF (cell ← FetchCell[design, name])=NIL THEN {
decoder, ram, rightPower: CellInstance;
cell ← CreateRecordCell[design: design, name: name];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd", "AccessB"]];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["AdrBit", "nAdrBit"], type: CreateWireSequenceType[design: design, count: addressDecoderBits]];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Bit", "nBit"], type: CreateWireSequenceType[design: design, count: select*columnOcts]];
[] ← CreateWire[design: design, in: cell, name: "Word", type: CreateWireSequenceType[design: design, count: 4*rowQuads]];
decoder ← CreateCellInstance[design: design, in: cell, type: CrossRAMDecoder.CreateDecoder[design: design, addressDecoderBits: addressDecoderBits, rowQuads: rowQuads]];
ram ← CreateCellInstance[design: design, in: cell, type: CrossRAMRAM.CreateRAM[design: design, columnOcts: columnOcts, rowQuads: rowQuads]];
rightPower ← CreateCellInstance[design: design, in: cell, type: CreateRightPowerSeq[design: design]];
PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, LIST[$AbutX, decoder, ram, rightPower]]];
};
};
Port: Vdd
CreateRightPowerSeq: PROC [design: Design] RETURNS [cell: CellType] = {
name: ROPE ← "RightPowerSeq";
IF (cell ← FetchCell[design, name])=NIL THEN {
cell ← CreateSequenceCell[design: design, name: name, baseCell: CreateRightPower[design: design], count: 2*rowQuads, attribute: [$GenLayout, $ArrayY]];
};
};
Port: Vdd
CreateRightPower: PROC [design: Design] RETURNS [cell: CellType] = {
name: ROPE ← "RightPower";
IF (cell ← FetchCell[design, name])=NIL THEN {
cell ← CreateRecordCell[design: design, name: name, attribute: [$GenLayout, $Get]];
[] ← CreatePublicWire[design: design, on: cell, name: "Vdd"];
};
};
END.