
    <<CrossRAMDecoderImpl.mesa>>
        <<Copyright © 1985 by Xerox Corporation.  All rights reserved.>>
        <<Barth, September 26, 1985 12:41:41 pm PDT>>
        <<Last Edited by: Louis Monier September 20, 1985 3:41:00 pm PDT>>
        <<>>
    DIRECTORY BitOps, CoreCreate, CoreMapFunction, CoreOps, CoreTransistor, CrossRAMDecoder, CrossRAMSSI, IO;

    CrossRAMDecoderImpl: CEDAR PROGRAM
        IMPORTS BitOps, CoreCreate, CoreMapFunction, CoreOps, CoreTransistor, CrossRAMSSI, IO
        EXPORTS CrossRAMDecoder = 
        BEGIN OPEN CoreCreate, CrossRAMDecoder;

    CreateDecoder: PUBLIC PROC [design: Design, addressDecoderBits, rowQuads: NAT] RETURNS [cell: CellType] = {
    name: ROPE _ "Decoder";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            rowPairs: NAT _ 2*rowQuads;
            andDecoderBits: NAT _ addressDecoderBits-1;
            decoderLeft, decoderAnd, decoderRight, decoderLogic: CellInstance;
            cell _ CreateRecordCell[design: design, name: name];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd", "AccessB"]];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["AdrBit", "nAdrBit"], type: CreateWireSequenceType[design: design, 
            count: addressDecoderBits]];
            [] _ CreatePublicWire[design: design, on: cell, name: "Word", type: CreateWireSequenceType[design: design, count: 2*rowPairs]];
            [] _ CreateWire[design: design, in: cell, name: "nDecode", type: CreateWireSequenceType[design: design, count: rowPairs]];
            decoderLeft _ CreateCellInstance[design: design, in: cell, type: CreateDecoderLeftColumn[design: design, rowQuads: rowQuads]];
            decoderAnd _ CreateCellInstance[design: design, in: cell, type: CreateDecoderAndPlane[design: design, andDecoderBits: 
            andDecoderBits, rowPairs: rowPairs], bind: IO.PutFR["AdrBit: AdrBit[0..%g), nAdrBit: nAdrBit[0..%g)", 
            IO.int[andDecoderBits], IO.int[andDecoderBits]]];
            decoderRight _ CreateCellInstance[design: design, in: cell, type: CreateDecoderRightColumn[design: design, rowQuads: rowQuads]];
            decoderLogic _ CreateCellInstance[design: design, in: cell, type: CreateDecoderLogicColumn[design: design, rowQuads: rowQuads], 
            bind: IO.PutFR["TreeSelect: [AdrBit[%g], nAdrBit[%g]]", IO.int[addressDecoderBits-1], IO.int[addressDecoderBits-1]]];
            PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, LIST[$AbutX, decoderLeft, decoderAnd, decoderRight, 
            decoderLogic]]];
            };
        };

<<Ports: Vdd, Gnd, AdrBit[0..andDecoderBits), nAdrBit[0..andDecoderBits), nDecode[0..rowPairs)>>
    CreateDecoderAndPlane: PROC [design: Design, andDecoderBits, rowPairs: NAT] RETURNS [cell: CellType] = {
        decoderCellType: CoreMapFunction.MapFnCellType _  NEW[CoreMapFunction.MapFnCellTypeRec[4]];
        decoderCellType.uy _ rowPairs-1;
        decoderCellType.ux _ andDecoderBits-1;
        decoderCellType.xyFn _ DecoderSelect;
        decoderCellType[0] _ CreateDecoderBit[design: design, zero: TRUE];
        decoderCellType[1] _ CreateDecoderBit[design: design, zero: FALSE];
        decoderCellType[2] _ CreateIdentityCell[design: design, name: "DecoderBitZeroFlipY", baseCell: decoderCellType[0], attribute: 
        [$GenLayout, $FlipY]];
        decoderCellType[3] _ CreateIdentityCell[design: design, name: "DecoderBitOneFlipY", baseCell: decoderCellType[1], attribute: 
        [$GenLayout, $FlipY]];
        cell _ CoreMapFunction.Create[name: "DecoderAndPlane", publicWire:
            CoreOps.CreateRecordWire[components: LIST[
                CoreOps.CreateAtomWire["Vdd"],
                CoreOps.CreateAtomWire["Gnd"],
                CoreOps.CreateSequenceWire["AdrBit", CoreOps.CreateAtomWire[], andDecoderBits],
                CoreOps.CreateSequenceWire["nAdrBit", CoreOps.CreateAtomWire[], andDecoderBits],
                CoreOps.CreateSequenceWire["nDecode", CoreOps.CreateAtomWire[], rowPairs]]],
             args: decoderCellType];
        CoreOps.InsertCellType[design: design, cellType: cell];
        PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, $MapFn]];
        };

    DecoderSelect: CoreMapFunction.XYFn = {
        oddWord: BOOL _ BitOps.EBFW[y, 1, 0];
        oddBit: BOOL _ BitOps.EBFW[y, args.ux, x];
        index _ BitOps.IBIW[oddWord, BitOps.IBIW[oddBit, BitOps.BitWordZero, 2, 1], 2, 0];
        };

<<Ports: Vdd, Gnd, AdrBit, nAdrBit, nDecode, nStackTop, nStackBottom>>
    CreateDecoderBit: PROC [design: Design, zero: BOOL] RETURNS [cell: CellType] = {
    name: ROPE _ IO.PutFR["Decoder%g", IO.rope[IF zero THEN "Zero" ELSE "One"]];
        IF (cell _ FetchCell[design, name])=NIL THEN {
            adrRope: ROPE _ IF zero THEN "nAdrBit" ELSE "AdrBit";
            cell _ CreateRecordCell[design: design, name: name, attribute: [$GenLayout, $Get]];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd", "AdrBit", "nAdrBit", "nDecode", "nStackTop", 
            "nStackBottom"]];
            [] _ CreateCellInstance[design: design, in: cell, type: CoreTransistor.Create[args: NEW[CoreTransistor.TransistorRec _ [type: 
            pE]]], bind: IO.PutFR["gate: %g, ch1: Vdd, ch2: nDecode", IO.rope[adrRope]]];
            [] _ CreateCellInstance[design: design, in: cell, type: CoreTransistor.Create[args: NEW[CoreTransistor.TransistorRec _ [type: 
            nE]]], bind: IO.PutFR["gate: %g, ch1: nStackTop, ch2: nStackBottom", IO.rope[adrRope]]];
            };
        };

<<Ports: Vdd, Gnd>>
    CreateDecoderLeftColumn: PUBLIC PROC [design: Design, rowQuads: NAT] RETURNS [cell: CellType] = {
    name: ROPE _ "DecoderLeftColumn";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            cell _ CreateSequenceCell[design: design, name: name, baseCell: CreateDecoderLeftPair[design: design], count: rowQuads, attribute: 
            [$GenLayout, $ArrayY]];
            };
        };

<<Ports: Vdd, Gnd>>
    CreateDecoderLeftPair: PUBLIC PROC [design: Design] RETURNS [cell: CellType] = {
    name: ROPE _ "DecoderLeftPair";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            decoderLeft: CellType _ CreateDecoderLeft[design: design];
            top, bottom: CellInstance;
            cell _ CreateRecordCell[design: design, name: name];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd"]];
            bottom _ CreateCellInstance[design: design, in: cell, type: decoderLeft];
            top _ CreateCellInstance[design: design, in: cell, type: CreateIdentityCell[design: design, name: "DecoderLeftFlipY", baseCell: 
            decoderLeft, attribute: [$GenLayout, $FlipY]]];
            PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, LIST[$AbutY, bottom, top]]];
            };
        };

<<Ports: Vdd, Gnd>>
    CreateDecoderLeft: PUBLIC PROC [design: Design] RETURNS [cell: CellType] = {
    name: ROPE _ "DecoderLeft";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            cell _ CreateRecordCell[design: design, name: name, attribute: [$GenLayout, $Get]];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd"]];
            };
        };

<<Ports: Vdd, nDecode[0..2*rowQuads)>>
    CreateDecoderRightColumn: PUBLIC PROC [design: Design, rowQuads: NAT] RETURNS [cell: CellType] = {
    name: ROPE _ "DecoderRightColumn";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            cell _ CreateSequenceCell[design: design, name: name, baseCell: CreateDecoderRightPair[design: design], count: rowQuads, 
            sequencePorts: LIST["nDecode"], attribute: [$GenLayout, $ArrayY]];
            };
        };

<<Ports: Vdd, nDecode[0..2)>>
    CreateDecoderRightPair: PUBLIC PROC [design: Design] RETURNS [cell: CellType] = {
    name: ROPE _ "DecoderRightPair";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            decoderRight: CellType _ CreateDecoderRight[design: design];
            top, bottom: CellInstance;
            cell _ CreateRecordCell[design: design, name: name];
            [] _ CreatePublicWire[design: design, on: cell, name: "Vdd"];
            [] _ CreatePublicWire[design: design, on: cell, name: "nDecode", type: CreateWireSequenceType[design: design, count: 2]];
            bottom _ CreateCellInstance[design: design, in: cell, type: decoderRight, bind: "nDecode: nDecode[0]"];
            top _ CreateCellInstance[design: design, in: cell, type: CreateIdentityCell[design: design, name: "DecoderRightFlipY", baseCell: 
            decoderRight, attribute: [$GenLayout, $FlipY]], bind: "nDecode: nDecode[1]"];
            PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, LIST[$AbutY, bottom, top]]];
            };
        };

<<Ports: Vdd, nDecode>>
    CreateDecoderRight: PUBLIC PROC [design: Design] RETURNS [cell: CellType] = {
    name: ROPE _ "DecoderRight";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            cell _ CreateRecordCell[design: design, name: name, attribute: [$GenLayout, $Get]];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "nDecode"]];
            };
        };

<<Ports: Vdd, Gnd, AccessB, TreeSelect[0..2), Word[0..4*rowQuads), nDecode[0..2*rowQuads)>>
    CreateDecoderLogicColumn: PUBLIC PROC [design: Design, rowQuads: NAT] RETURNS [cell: CellType] = {
    name: ROPE _ "DecoderLogicColumn";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            cell _ CreateSequenceCell[design: design, name: name, baseCell: CreateDecoderLogicPair[design: design], count: rowQuads, 
            sequencePorts: LIST["nDecode", "Word"], attribute: [$GenLayout, $ArrayY]];
            };
        };

<<Ports: Vdd, Gnd, AccessB, TreeSelect[0..2), Word[0..4), nDecode[0..2)>>
    CreateDecoderLogicPair: PROC [design: Design] RETURNS [cell: CellType] = {
    name: ROPE _ "DecoderLogicPair";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            decoderLogic: CellType _ CreateDecoderLogic[design: design];
            top, bottom: CellInstance;
            cell _ CreateRecordCell[design: design, name: name];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd", "AccessB"]];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["TreeSelect", "nDecode"], type: CreateWireSequenceType[design: design, 
            count: 2]];
            [] _ CreatePublicWire[design: design, on: cell, name: "Word", type: CreateWireSequenceType[design: design, count: 4]];
            bottom _ CreateCellInstance[design: design, in: cell, type: decoderLogic, bind: "Word: [Word[0], Word[1]], nDecode: nDecode[0]"];
            top _ CreateCellInstance[design: design, in: cell, type: CreateIdentityCell[design: design, name: "DecoderLogicFlipY", baseCell: 
            decoderLogic, attribute: [$GenLayout, $FlipY]], bind: "Word: [Word[2], Word[3]], nDecode: nDecode[1]"];
            PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, LIST[$AbutY, bottom, top]]];
            };
        };

<<Ports: Vdd, Gnd, AccessB, TreeSelect[0..2), Word[0..2), nDecode>>
    CreateDecoderLogic: PROC [design: Design] RETURNS [cell: CellType] = {
    name: ROPE _ "DecoderLogic";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            cell _ CreateSequenceCell[design: design, name: name, baseCell: CreateWordDriver[design: design], count: 2, sequencePorts: 
            LIST["TreeSelect", "Word"], attribute: [$GenLayout, $Get]];
            };
        };

<<Ports: Vdd, Gnd, AccessB, TreeSelect, Word, nDecode>>
    CreateWordDriver: PROC [design: Design] RETURNS [cell: CellType] = {
    name: ROPE _ "WordDriver";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            cell _ CreateRecordCell[design: design, name: name];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd", "AccessB", "TreeSelect", "Word", "nDecode"]];
            [] _ CreateWire[design: design, in: cell, names: LIST["nTreeDecode", "Decode", "nWord", "WordStack"]];
            [] _ CreateCellInstance[design: design, in: cell, type: CrossRAMSSI.CreateInverter[design: design], bindings: LIST["Input: 
            nTreeDecode, Output: Decode", "Input: nWord, Output: Word"]];
            [] _ CreateCellInstance[design: design, in: cell, type: CoreTransistor.Create[args: NEW[CoreTransistor.TransistorRec _ [type: 
            nE]]], bindings: LIST["gate: Decode, ch1: nWord, ch2: WordStack", "gate: AccessB, ch1: WordStack, ch2: Gnd", "gate: 
            TreeSelect, ch1: nDecode, ch2: nTreeDecode"]];
            [] _ CreateCellInstance[design: design, in: cell, type: CoreTransistor.Create[args: NEW[CoreTransistor.TransistorRec _ [type: 
            pE]]], bindings: LIST["gate: AccessB, ch1: Vdd, ch2: nWord", "gate: TreeSelect, ch1: Vdd, ch2: nTreeDecode"]];
            };
        };

    END.