
    <<CrossRAMDataBufferImpl.mesa>>
        <<Copyright © 1985 by Xerox Corporation.  All rights reserved.>>
        <<Barth, September 20, 1985 2:12:36 pm PDT>>
        <<Louis Monier September 20, 1985 3:22:14 pm PDT>>
        <<>>
    DIRECTORY CoreCreate, CoreMapFunction, CoreOps, CoreTransistor, CrossRAMDataBuffer, CrossRAMSSI, IO;

    CrossRAMDataBufferImpl: CEDAR PROGRAM
        IMPORTS CoreCreate, CoreMapFunction, CoreOps, CoreTransistor, CrossRAMSSI, IO
        EXPORTS CrossRAMDataBuffer
        = BEGIN OPEN CoreCreate, CrossRAMDataBuffer;

    CreateDataBuffer: PUBLIC PROC [design: Design, select, columnOcts: NAT] RETURNS [cell: CellType] = {
    name: ROPE _ "DataBuffer";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            cell _ CreateSequenceCell[design: design, name: name, baseCell: CreateDataBufferBit[design: design, select: select], count: 
            columnOcts, sequencePorts: LIST["Bit", "nBit", "DataB"], attribute: [$GenLayout, $ArrayX]];
            };
        };

<<Ports: Vdd, Gnd, WriteB, nWriteB, ReadB, nReadB, DataB, Select[0..select), Bit[0..select), nBit[0..select)>>
    CreateDataBufferBit: PUBLIC PROC [design: Design, select: NAT] RETURNS [cell: CellType] = {
    name: ROPE _ "DataBufferBit";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            oct, stitch: CellInstance;
            cell _ CreateRecordCell[design: design, name: name];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd", "WriteB", "nWriteB", "ReadB", "nReadB", "DataB"]];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["Select", "Bit", "nBit"], type: CreateWireSequenceType[design: design, 
            count: select]];
            oct _ CreateCellInstance[design: design, in: cell, type: CreateDataBufferOct[design: design, select: select]];
            stitch _ CreateCellInstance[design: design, in: cell, type: CreateDecoderStitch[design: design, select: select]];
            PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, LIST[$AbutX, oct, stitch]]];
            };
        };

<<Ports: Vdd, Gnd, WriteB, nWriteB, ReadB, nReadB, DataB, Select[0..select), Bit[0..select), nBit[0..select)>>
    CreateDataBufferOct: PROC [design: Design, select: NAT] RETURNS [cell: CellType] = {
    name: ROPE _ "DataBufferOct";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            connectSeq, muxSelect, mux, bitDrive: CellInstance;
            cell _ CreateRecordCell[design: design, name: name];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd", "WriteB", "nWriteB", "ReadB", "nReadB", "DataB"]];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["Select", "Bit", "nBit"], type: CreateWireSequenceType[design: design, 
            count: select]];
            [] _ CreateWire[design: design, in: cell, names: LIST["Buffer", "nBuffer"]];
            connectSeq _ CreateCellInstance[design: design, in: cell, type: CreateSequenceCell[design: design, name: "BitLineConnectSeq", 
            baseCell: CreateBitLineConnect[design: design], count: select, sequencePorts: LIST["Bit", "nBit"], attribute: 
            [$GenLayout, $ArrayX]]];
            muxSelect _ CreateCellInstance[design: design, in: cell, type: CreateDataBufferMuxSelect[design: design, select: select]];
            mux _ CreateCellInstance[design: design, in: cell, type: CreateDataBufferMux[design: design, select: select]];
            bitDrive _ CreateCellInstance[design: design, in: cell, type: CreateBitDrive[design: design]];
            PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, LIST[$AbutY, connectSeq, muxSelect, mux, bitDrive]]];
            };
        };

<<Ports: Gnd, Select[0..select), Bit[0..select), nBit[0..select), Buffer, nBuffer>>
    CreateDataBufferMux: PUBLIC PROC [design: Design, select: NAT] RETURNS [cell: CellType] = {
    name: ROPE _ "DataBufferMuxBit";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            bitMuxEnd, bitMuxSeq: CellInstance;
            bitMuxBit: CellType _ CreateBitMuxBit[design: design];
            cell _ CreateRecordCell[design: design, name: name];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["Gnd", "Buffer", "nBuffer"]];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["Select", "Bit", "nBit"], type: CreateWireSequenceType[design: design, 
            count: select]];
            bitMuxEnd _ CreateCellInstance[design: design, in: cell, type: CreateIdentityCell[design: design, name: "BitMuxEnd", baseCell: 
            bitMuxBit, attribute: [$GenLayout, $Get]], bind: "Select: Select[0], Bit: Bit[0], nBit: nBit[0]"];
            bitMuxSeq _ CreateCellInstance[design: design, in: cell, type: CreateSequenceCell[design: design, name: "BitMuxSeq", baseCell: 
            CreateIdentityCell[design: design, name: "BitMux", baseCell: bitMuxBit, attribute: [$GenLayout, $Get]], count: 
            select-1, sequencePorts: LIST["Select", "Bit", "nBit"], attribute: [$GenLayout, $ArrayX]], bind: IO.PutFR["Select: 
            Select[1..%g), Bit: Bit[1..%g), nBit: nBit[1..%g)", IO.int[select], IO.int[select], IO.int[select]]];
            PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, LIST[$AbutX, bitMuxEnd, bitMuxSeq]]];
            };
        };

<<Ports: Gnd, Select, Bit, nBit, Buffer, nBuffer >>
    CreateBitMuxBit: PROC [design: Design] RETURNS [cell: CellType] = {
    name: ROPE _ "BitMuxBit";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            cell _ CreateRecordCell[design: design, name: name];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["Gnd", "Select", "Bit", "nBit", "Buffer", "nBuffer"]];
            [] _ CreateCellInstance[design: design, in: cell, type: CoreTransistor.Create[args: NEW[CoreTransistor.TransistorRec _ [type: 
            nE]]], bindings: LIST["gate: Select, ch1: Bit, ch2: Buffer", "gate: Select, ch1: nBit, ch2: nBuffer"]];
            };
        };

<<Ports: Gnd, Select[0..select), Bit[0..select), nBit[0..select)>>
    CreateDataBufferMuxSelect: PUBLIC PROC [design: Design, select: NAT] RETURNS [cell: CellType] = {
    name: ROPE _ "DataBufferMux";
        bitSel: CellType _ CreateBitSel[design: design];
        muxCellType: CoreMapFunction.MapFnCellType _  NEW[CoreMapFunction.MapFnCellTypeRec[3]];
        muxCellType.ux _ select;
        muxCellType.uy _ select;
        muxCellType.xyFn _ MuxSelect;
        muxCellType[BitSelNoPoly] _ CreateIdentityCell[design: design, name: "BitSelNoPoly", baseCell: bitSel, attribute: [$GenLayout, 
        $Get]];
        muxCellType[BitSelContact] _ CreateIdentityCell[design: design, name: "BitSelContact", baseCell: bitSel, attribute: [$GenLayout, 
        $Get]];
        muxCellType[BitSelPoly] _ CreateBitSelPoly[design: design];
        cell _ CoreMapFunction.Create[
            name: name,
            publicWire: CoreOps.CreateRecordWire[components: LIST [
                CoreOps.CreateAtomWire[name: "Gnd"],
                CoreOps.CreateSequenceWire[name: "Select", base: CoreOps.CreateAtomWire[], count: select],
                CoreOps.CreateSequenceWire[name: "Bit", base: CoreOps.CreateAtomWire[], count: select],
                CoreOps.CreateSequenceWire[name: "nBit", base: CoreOps.CreateAtomWire[], count: select]]],
            args: muxCellType];
        CoreOps.InsertCellType[design: design, cellType: cell];
        PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, $MapFn]];
        };

    BitSelNoPoly: NAT = 0;
    BitSelContact: NAT = 1;
    BitSelPoly: NAT = 2;

    MuxSelect: CoreMapFunction.XYFn = {
        IF y>x THEN RETURN[BitSelNoPoly];
        IF y=x THEN RETURN[BitSelContact];
        IF y<x THEN RETURN[BitSelPoly];
        };

<<Ports: Vdd, Gnd, WriteB, nWriteB, ReadB, nReadB, DataB, Buffer, nBuffer>>
    CreateBitDrive: PUBLIC PROC [design: Design] RETURNS [cell: CellType] = {
    name: ROPE _ "BitDrive";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            cell _ CreateRecordCell[design: design, name: name, attribute: [$GenLayout, $Get]];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd", "WriteB", "nWriteB", "ReadB", "nReadB", "DataB", 
            "Buffer", "nBuffer"]];
            [] _ CreateWire[design: design, in: cell, name: "ndatab"];
            [] _ CreateCellInstance[design: design, in: cell, type: CrossRAMSSI.CreateInverter[design: design], bind: "Input: DataB, Output: 
            ndatab"];
            [] _ CreateCellInstance[design: design, in: cell, type: CrossRAMSSI.CreateTristateBuffer[design: design], bindings: LIST["nInput: 
            nBuffer, Drive: ReadB, nDrive: nReadB, Output: DataB", "nInput: DataB, Drive: WriteB, nDrive: nWriteB, Output: 
            nBuffer", "nInput: ndatab, Drive: WriteB, nDrive: nWriteB, Output: Buffer"]];
            };
        };

<<Ports: Gnd, Select, Bit, nBit >>
    CreateBitSel: PROC [design: Design] RETURNS [cell: CellType] = {
    name: ROPE _ "BitSel";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            cell _ CreateRecordCell[design: design, name: name];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["Gnd", "Select", "Bit", "nBit"]];
            };
        };

<<Ports: Gnd, Select, Bit, nBit, OtherSelect >>
    CreateBitSelPoly: PROC [design: Design] RETURNS [cell: CellType] = {
    name: ROPE _ "BitSelPoly";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            cell _ CreateRecordCell[design: design, name: name, attribute: [$GenLayout, $Get]];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["Gnd", "Select", "Bit", "nBit", "OtherSelect"]];
            };
        };

<<Ports: Gnd, Bit, nBit >>
    CreateBitLineConnect: PROC [design: Design] RETURNS [cell: CellType] = {
    name: ROPE _ "BitLineConnect";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            cell _ CreateRecordCell[design: design, name: name, attribute: [$GenLayout, $Get]];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["Gnd", "Bit", "nBit"]];
            };
        };

<<Ports: Vdd, Gnd, WriteB, nWriteB, ReadB, nReadB, Select[0..select)>>
    CreateDecoderStitch: PROC [design: Design, select: NAT] RETURNS [cell: CellType] = {
    name: ROPE _ "DecoderStitch";
        IF (cell _ FetchCell[design, name])=NIL THEN {
            cell _ CreateRecordCell[design: design, name: name, attribute: [$GenLayout, $Get]];
            [] _ CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "Gnd", "WriteB", "nWriteB", "ReadB", "nReadB"]];
            [] _ CreatePublicWire[design: design, on: cell, name: "Select", type: CreateWireSequenceType[design: design, count: select]];
            };
        };

    END.