CrossRAMBottomImpl.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Barth, September 4, 1985 2:16:20 pm PDT
Louis Monier September 12, 1985 2:50:49 pm PDT
DIRECTORY CoreCreate, CoreTransistor, CrossRAMBottom;
CrossRAMBottomImpl:
CEDAR
PROGRAM
IMPORTS CoreCreate, CoreTransistor
EXPORTS CrossRAMBottom =
BEGIN OPEN CoreCreate, CrossRAMBottom;
CreateBottom:
PUBLIC
PROC [design: Design, columnOcts, addressDecoderBits:
NAT]
RETURNS [cell: CellType] = {
name: ROPE ← "Bottom";
IF (cell ← FetchCell[design, name])=
NIL
THEN {
decoderLeft, decoderSeq, decoderRight, precharge, bottomRight: CellInstance;
cell ← CreateRecordCell[design: design, name: name];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "nPrechargeB", "AccessB"]];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Bit", "nBit"], type: CreateWireSequenceType[design: design, count: 8*columnOcts]];
decoderLeft ← CreateCellInstance[design: design, in: cell, type: CreateBottomDecoderLeft[design: design]];
decoderSeq ← CreateCellInstance[design: design, in: cell, type: CreateDecoderSeq[design: design, addressDecoderBits: addressDecoderBits]];
decoderRight ← CreateCellInstance[design: design, in: cell, type: CreateBottomDecoderRight[design: design]];
precharge ← CreateCellInstance[design: design, in: cell, type: CreatePrecharge[design: design, columnOcts: columnOcts]];
bottomRight ← CreateCellInstance[design: design, in: cell, type: CreateBottomRight[design: design]];
PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, LIST[$AbutX, decoderLeft, decoderSeq, decoderRight, precharge, bottomRight]]];
};
};
Ports: Vdd
CreateDecoderSeq:
PROC [design: Design, addressDecoderBits:
NAT]
RETURNS [cell: CellType] = {
name: ROPE ← "DecoderSeq";
IF (cell ← FetchCell[design, name])=
NIL
THEN {
cell ← CreateSequenceCell[design: design, name: name, baseCell: CreateBottomDecoder[design: design], count: addressDecoderBits, attribute: [$GenLayout, $ArrayX]];
};
};
Port: Vdd
CreateBottomDecoder:
PROC [design: Design]
RETURNS [cell: CellType] = {
name: ROPE ← "BottomDecoder";
IF (cell ← FetchCell[design, name])=
NIL
THEN {
cell ← CreateRecordCell[design: design, name: name, attribute: [$GenLayout, $Get]];
[] ← CreatePublicWire[design: design, on: cell, name: "Vdd"];
};
};
Port: Vdd
CreateBottomDecoderLeft:
PROC [design: Design]
RETURNS [cell: CellType] = {
name: ROPE ← "BottomDecoderLeft";
IF (cell ← FetchCell[design, name])=
NIL
THEN {
cell ← CreateRecordCell[design: design, name: name, attribute: [$GenLayout, $Get]];
[] ← CreatePublicWire[design: design, on: cell, name: "Vdd"];
};
};
Ports: Vdd, nPrechargeB, AccessB
CreateBottomDecoderRight:
PROC [design: Design]
RETURNS [cell: CellType] = {
name: ROPE ← "BottomDecoderRight";
IF (cell ← FetchCell[design, name])=
NIL
THEN {
cell ← CreateRecordCell[design: design, name: name, attribute: [$GenLayout, $Get]];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "nPrechargeB", "AccessB"]];
};
};
Port: Vdd
CreateBottomRight:
PROC [design: Design]
RETURNS [cell: CellType] = {
name: ROPE ← "BottomRight";
IF (cell ← FetchCell[design, name])=
NIL
THEN {
cell ← CreateRecordCell[design: design, name: name, attribute: [$GenLayout, $Get]];
[] ← CreatePublicWire[design: design, on: cell, name: "Vdd"];
};
};
Ports: Vdd, nPrechargeB, Bit[0..8*columnOcts), nBit[0..8*columnOcts)
CreatePrecharge:
PROC [design: Design, columnOcts:
NAT]
RETURNS [cell: CellType] = {
name: ROPE ← "Precharge";
IF (cell ← FetchCell[design, name])=
NIL
THEN {
cell ← CreateSequenceCell[design: design, name: name, baseCell: CreatePrechargeOctStitch[design: design], count: columnOcts, sequencePorts: LIST["Bit", "nBit"], attribute: [$GenLayout, $ArrayX]];
};
};
Ports: Vdd, nPrechargeB, Bit[0..8), nBit[0..8)
CreatePrechargeOctStitch:
PROC [design: Design, static:
BOOL ←
TRUE]
RETURNS [cell: CellType] = {
name: ROPE ← "PrechargeOctStitch";
IF (cell ← FetchCell[design, name])=
NIL
THEN {
octet, stitch: CellInstance;
cell ← CreateRecordCell[design: design, name: name];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "nPrechargeB"]];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Bit", "nBit"], type: CreateWireSequenceType[design: design, count: 8]];
octet ← CreateCellInstance[design: design, in: cell, type: CreatePrechargeOct[design: design]];
stitch ← CreateCellInstance[design: design, in: cell, type: CreatePrechargeStitch[design: design]];
PutAttributeOnCell[design: design, on: cell, attribute: [$GenLayout, LIST[$AbutX, octet, stitch]]];
};
};
Ports: Vdd, nPrechargeB, Bit[0..8), nBit[0..8)
CreatePrechargeOct:
PROC [design: Design]
RETURNS [cell: CellType] = {
name: ROPE ← "PrechargeOct";
IF (cell ← FetchCell[design, name])=
NIL
THEN {
cell ← CreateSequenceCell[design: design, name: name, baseCell: CreatePrechargeSlice[design: design], count: 8, sequencePorts: LIST["Bit", "nBit"], attribute: [$GenLayout, $ArrayX]];
};
};
Ports: Vdd, nPrechargeB
CreatePrechargeStitch:
PROC [design: Design]
RETURNS [cell: CellType] = {
name: ROPE ← "PrechargeStich";
IF (cell ← FetchCell[design, name])=
NIL
THEN {
cell ← CreateRecordCell[design: design, name: name, attribute: [$GenLayout, $Get]];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "nPrechargeB"]];
};
};
Ports: Vdd, nPrechargeB, Bit, nBit
CreatePrechargeSlice:
PROC [design: Design]
RETURNS [cell: CellType] = {
name: ROPE ← "PrechargeSlice";
IF (cell ← FetchCell[design, name])=
NIL
THEN {
cell ← CreateRecordCell[design: design, name: name, attribute: [$GenLayout, $Get]];
[] ← CreatePublicWire[design: design, on: cell, names: LIST["Vdd", "nPrechargeB", "Bit", "nBit"]];
[] ← CreateCellInstance[design: design, in: cell, type: CoreTransistor.Create[args: NEW[CoreTransistor.TransistorRec ← [type: pE]]], bindings: LIST["gate: nPrechargeB, ch1: Bit, ch2: Vdd", "gate: nPrechargeB, ch1: nBit, ch2: Vdd"]];
};
};
END.