CrossRAMTest.mesa
Barth, March 25, 1986 11:39:53 am PST
DIRECTORY Core, CrossRAM, Ports, Rosemary, RosemaryUser;
CrossRAMTest:
CEDAR
PROGRAM
IMPORTS Ports, Rosemary, RosemaryUser =
BEGIN OPEN CrossRAM;
Init:
PROC [ct: Core.CellType] = {
[] ← Rosemary.SetFixedWire[ct.public[Vdd], H];
[] ← Rosemary.SetFixedWire[ct.public[Gnd], L];
[] ← Rosemary.SetFixedWire[ct.public[PadVdd], H];
[] ← Rosemary.SetFixedWire[ct.public[PadGnd], L];
[] ← Ports.InitTesterDrive[wire: ct.public[nPrecharge], initDrive: force];
[] ← Ports.InitTesterDrive[wire: ct.public[Access], initDrive: force];
[] ← Ports.InitTesterDrive[wire: ct.public[Write], initDrive: force];
[] ← Ports.InitTesterDrive[wire: ct.public[Read], initDrive: force];
[] ← Ports.InitTesterDrive[wire: ct.public[Address], initDrive: force];
[] ← Ports.InitTesterDrive[wire: ct.public[Data], initDrive: none];
[] ← RosemaryUser.MakeStandardViewer[name: "CrossRAM Tester", cellType: ct, testButtons: LIST[["Write2Read2", Write2Read2]], displayWires: RosemaryUser.DisplayPortLeafWires[wire: ct.public]];
};
Write2Read2: RosemaryUser.TestProc = {
AccessRAM:
PROC [write:
BOOL, address:
CARDINAL, data:
CARDINAL] = {
p[Address].c ← address;
precharge
p[nPrecharge].b ← FALSE;
Eval[];
p[nPrecharge].b ← TRUE;
Eval[];
enable select line
p[Access].b ← TRUE;
if write then enable write drivers
IF write
THEN {
p[Data].d ← force;
p[Write].b ← TRUE;
}
ELSE {
p[Data].d ← expect;
p[Read].b ← TRUE;
};
p[Data].c ← data;
Eval[];
disable select line
p[Access].b ← p[Write].b ← p[Read].b ← FALSE;
p[Data].d ← none;
Eval[];
};
p[Vdd].b ← TRUE; p[Gnd].b ← FALSE;
p[PadVdd].b ← TRUE; p[PadGnd].b ← FALSE;
p[nPrecharge].b ← TRUE; p[Access].b ← FALSE;
p[Write].b ← FALSE; p[Read].b ← FALSE;
Eval[! Rosemary.Stop => RESUME];
AccessRAM[write: TRUE, address: 0, data: 0];
AccessRAM[write: TRUE, address: 1, data: 0FFH];
AccessRAM[write: FALSE, address: 0, data: 0];
AccessRAM[write: FALSE, address: 1, data: 0FFH];
};
END.