CrossRAMImpl.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Barth, February 19, 1986 10:55:44 am PST
Louis Monier September 20, 1985 3:46:52 pm PDT
Bertrand Serlet December 9, 1985 11:43:24 am PST
Hoel, December 5, 1985 8:19:34 pm PST
DIRECTORY CoreCreate, CrossRAM, Ports, Rosemary;
CrossRAMImpl:
CEDAR
PROGRAM
IMPORTS CoreCreate, Ports, Rosemary
EXPORTS CrossRAM =
BEGIN OPEN CrossRAM, CoreCreate;
When changing these parameters change the pins in the cell library.
dataBits: INT = 15;
addressBits: INT = 11;
rowQuads: INT = 58;
columnOcts: INT = dataBits;
select: INT = 8;
log2Select: INT = 3;
addressDecoderBits: INT = 8;
AddressIndex: TYPE = [0..addressBits);
DataIndex: TYPE = [0..dataBits);
CrossRAMName: ROPE = "CrossRAM";
CrossRAMRoseClass:
ROPE = Rosemary.Register[roseClassName: CrossRAMName, init: CrossRAMInit, evalSimple: CrossRAMSimple];
CreateCrossRAM:
PUBLIC
PROC
RETURNS [cellType: CellType] = {
cellType ← Cell[
name: CrossRAMName,
public: Wires["Vdd", "Gnd", "PadVdd", "PadGnd", "nPrecharge", "Access", "Write", "Read", Seq["Address", addressBits], Seq["Data", dataBits]],
onlyInternal: Wires["nPrechargeB", "AccessB", "WriteB", "nWriteB", "ReadB", "nReadB", Seq["AddressB", addressBits], Seq["DataB", dataBits]],
instances: NIL];
[] ← Ports.InitPort[wire: cellType.public[Address], initType: c];
[] ← Ports.InitPort[wire: cellType.public[Data], initType: c];
[] ← Rosemary.BindCellType[cellType: cellType, roseClassName: CrossRAMRoseClass];
};
CrossRAMInit: Rosemary.InitProc = {
stateAny ← NEW[CrossRAMStateRec[4*rowQuads]];
IF dataBits>16 OR addressBits>16 THEN ERROR;
};
CrossRAMSimple: Rosemary.EvalProc = {
state: CrossRAMState ← NARROW[stateAny];
IF NOT p[Vdd].b OR p[Gnd].b OR NOT p[PadVdd].b OR p[PadGnd].b THEN SIGNAL Rosemary.Stop[];
IF (NOT p[nPrecharge].b AND p[Access].b) OR (p[Write].b AND p[Read].b) OR (NOT p[nPrecharge].b AND p[Write].b) THEN SIGNAL Rosemary.Stop[];
IF NOT p[nPrecharge].b THEN state.precharged ← TRUE;
p[Data].d ← none;
IF p[Access].b
THEN {
IF NOT state.precharged THEN SIGNAL Rosemary.Stop[];
IF state.accessOccured AND state.address#p[Address].c THEN SIGNAL Rosemary.Stop[];
state.accessOccured ← TRUE;
state.address ← p[Address].c;
IF p[Read].b
THEN {
p[Data].c ← state.memory[state.address].data;
p[Data].d ← drive;
};
IF p[Write].b THEN state.memory[state.address].data ← p[Data].c;
};
IF
NOT p[Access].b
AND state.accessOccured
THEN {
state.accessOccured ← FALSE;
state.precharged ← FALSE;
};
};
END.