DIRECTORY Core, CoreCompose, CoreOps, CrossRAM, Ports, Rosemary; CrossRAMTest: CEDAR PROGRAM IMPORTS CoreCompose, CoreOps, Ports, Rosemary = BEGIN OPEN CrossRAM; TestEvalProc: TYPE = PROC; TestCrossRAM: PUBLIC PROC = { context: CoreCompose.Context _ CoreCompose.CreateContext[]; ct: Core.CellType _ CoreCompose.CreateStructure["CrossRAM", context]; tw: Core.Wire _ CoreOps.CopyWire[ct.public]; testPort: Ports.Port; intermediatePort: Ports.Port; simulation: Rosemary.Simulation; Eval: TestEvalProc = { Ports.CopyPortValue[from: testPort, to: intermediatePort]; Rosemary.Settle[simulation]; Ports.CheckPortValue[truth: testPort, question: intermediatePort]; }; Ports.InitPort[wire: tw[Vdd], initDrive: infinite]; Ports.InitPort[wire: tw[Gnd], initDrive: infinite]; Ports.InitPort[wire: tw[PadVdd], initDrive: infinite]; Ports.InitPort[wire: tw[PadGnd], initDrive: infinite]; Ports.InitPort[wire: tw[nPrecharge], initDrive: force]; Ports.InitPort[wire: tw[Access], initDrive: force]; Ports.InitPort[wire: tw[Write], initDrive: force]; Ports.InitPort[wire: tw[Read], initDrive: force]; Ports.InitPort[wire: tw[Address], initType: c, initDrive: force]; Ports.InitPort[wire: tw[Data], initType: c, initDrive: none]; testPort _ Ports.CreatePort[tw]; intermediatePort _ Ports.CreatePort[tw]; simulation _ Rosemary.InstantiateCellType[ct, intermediatePort]; Write2Read2[testPort, Eval]; }; Write2Read2: PROC [p: Ports.Port, Eval: TestEvalProc] = { AccessRAM: PROC [write: BOOL, address: CARDINAL, data: CARDINAL] = { p[Address].c _ address; p[nPrecharge].b _ FALSE; Eval[]; p[nPrecharge].b _ TRUE; Eval[]; p[Access].b _ TRUE; IF write THEN { p[Data].d _ force; p[Write].b _ TRUE; } ELSE { p[Data].d _ expect; p[Read].b _ TRUE; }; p[Data].c _ data; Eval[]; p[Access].b _ p[Write].b _ p[Read].b _ FALSE; p[Data].d _ none; Eval[]; }; p[Vdd].b _ TRUE; p[Gnd].b _ FALSE; p[PadVdd].b _ TRUE; p[PadGnd].b _ FALSE; p[nPrecharge].b _ TRUE; p[Access].b _ FALSE; p[Write].b _ FALSE; p[Read].b _ FALSE; Eval[! Rosemary.Stop => RESUME]; AccessRAM[write: TRUE, address: 0, data: 0]; AccessRAM[write: TRUE, address: 1, data: 0FFH]; AccessRAM[write: FALSE, address: 0, data: 0]; AccessRAM[write: FALSE, address: 1, data: 0FFH]; }; END. τCrossRAMTest.mesa Barth, December 13, 1985 5:15:04 pm PST simulation _ Rosemary.InstantiateInstances[&ct, "JustAboveTransistors", intermediatePort]; precharge enable select line if write then enable write drivers disable select line Κ©˜codešœ™K™'—K˜KšΟk œ7˜@K˜šΟn œœ˜Kšœ(˜/Kšœœ ˜—K˜Kšž œœœ˜K˜šž œœœ˜Kšœ<˜