CrossRAM03 Revision Status February 9, 1986 Introduction Late last week, we realized that the revision history of CrossRAM03 had gotten intricate enough that someone had better document it. In particular, we wanted to make sure that the VTI run had the right revision level for each layer. Revision Summary The following table summarizes the revisions of CrossRAM03. The files for CrossRAM03 have names of the form MPC5NV., where: = A, R, S, or T; = 10, 21, 22, 23, 24, 30, 40, 50, 70, 80, 60, or 71; = AA or BA. # A R S T Mask Description 10 A R T thinOx 21 A R nWell 22 A R pWell (p field implant) 23 A R T nImp 24 A R T pImp 30 A R poly 40 A (R) T cut 50 A (R) metal 70 A (R) S cut2 (via) 80 A (R) T metal2 60 A (R) glass (oxide passivation) 71 nitride Note: "(R)" indicates that files were generated, but were identical to their "A" predecessors. Chip Summary The next table shows the appropriate revision per layer for the following chips: I1: CrossRAM03 as fabricated by ICL on run MPC5NA; V1: CrossRAM03 as to be fabricated by VTI; I2: CrossRAM03 as it might in the future be fabricated by ICL. # I1 V1 I2 Mask Description 10 A T T? thinOx 21 A R A? nWell 22 A R A? pWell (p field implant) 23 R T T? nImp 24 R T T? pImp 30 A R R? poly 40 A T ? cut 50 A A A metal 70 S S S cut2 (via) 80 A T T metal2 60 A A A glass (oxide passivation) 71 nitride For the VTI run, the required mask plates already exist, except for the five "T" layers: thinOx, nImp, pImp, cut, and metal2. As the table indicates, there are some unanswered questions about chip I2, if any: 1. Can ICL and VTI agree on a common biasing for nWell and pWell? If so, is it the biasing used on revision R? 2. Can ICL and VTI agree on a common biasing for nImp and pImp? If so, is it the biasing used on revision T? 3. Can ICL and VTI agree on a common biasing for thinOx? If so, is it the biasing used on revision T? 4. Can ICL and VTI agree on a common biasing for poly? If so, is it the biasing used on revision R? 5. Must ICL and VTI disagree on a common biasing for cut? It seems likely the ICL needs a biasing of zero. That would require making a new revision. Revision Details Revision A Revision A is the first revision of CrossRAM03. It used ICL's recommended biasing. Actually, we decided to forego the opportunity to try biasing recommended by VTI where we thought it could be made to work, because there would have been difficulties it applying the new biases to the chips on the run which were not specified in ChipnDale. We'd still like to try the VTI biases at ICL at some future time. 1. The thinOx bias was 0.5 microns per side, not 0.75 microns. 2. The poly bias was 0.0 microns per side, not 0.25 microns. Revision R Revision R was made for two reasons: 1. The nImp and pImp layers were "denotched," after adding a DeNotch capability to the CDMEBES22 software. DeNotching removes all shapes smaller than a specified width and also removes all spaces smaller than a specified width. This was necessary because the nImp layer of Revision A had some 0.5-micron (clear) spaces that couldn't be resolved uniformly on the mask plate, and therefore were partially filled with random spots. As a result, the KLA defect checking equipment found too many defects of this type to be much good at finding "real" defects. The pImp mask had some 0.5-micron (dark) shapes, which didn't seem to faze the KLA equipment, but we didn't like them anyhow. (Due to an error in the job deck, the nImp and pImp masks had to be made again anyway, so we decided to DeNotch both nImp and pImp first.) 2. We needed "VTI biasing" of the thinOx, poly, nWell, and pWell layers for chip V1. The biasing wasn't exactly the same as that recommended by VTI at the time, but we thought it was close enough. 3. Note that there were no design changes to CrossRAM03. Revision S Revision S was made for only one reason: to fix a design error in an output pad cell. Only the via layer was affected. The error was caught by a desk check and the fix was made in time to be incorporated into first CrossRAM03 chip fabricated by ICL (i.e., chip I1). Revision T Revision T was made for a number of reasons: 1. Electrical testing of chip I1 revealed the word lines were shorted to VDD. The fix involved removing an unwanted split contact, which affected the thinOx, nImp, pImp, and cut layers. (Actually, the fix was done so as to avoid having to change the nImp and pImp layers, but they ended up having to be changed for another reason; see item 4c below.) (A static connectivity checker would have caught this error. We didn't have one last December when Revision A was made, but the new Core software will have one.) 2. A desk check revealed that the interface between the DecoderLogic cells and *RamTwoBits cells had some 0.5-micron errors in metal2, involving some design rule violations of both minimum width and minimum spacing. (They were not caught earlier because Spinifex ran out of virtual memory trying to check the entire chip, and I didn't think of trying to check some of the larger cells. The CrossRAMCellLibrary was checked by Spinifex and had no DRC errors. The error was introduced because core/patchwork flipped some of the DecoderLogic cells but none of the *RamTwoBits cells. That placed a symmetry requirement on those cells of which I was unaware, so I made them asymmetric.) 3. A bug in the CDMEBES DeNotch function was discovered; it had been undersizing shapes by 0.75 microns per side. The bug was fixed. We think that only the CrossRAM03 used this DeNotch function, and we know only the nImp and pImp layers were affected. (See also item 4c below.) 4. VTI biasing: a. VTI's latest Tooling Specification, 02-10001, Rev *C, required a change of the thinOx biasing to 0.75 microns per side. (This was the latest in a series of flip-flops between 0.75 microns and 0.9 microns per side. You probably don't want to know the details. But this time we think we've got it right.) b. We (Bob Allen) decided to take VTI's biasing for the cut layer seriously. It's -0.25 microns per side on the mag tape, and -0.15 microns per side on the mask plate. We had been hoping to use 0.0 microns per side, the same as ICL, so we could share this mask between ICL and VTI. (ICL almost certainly can't use this bias on their P&E 341 projection aligner.) c. We also decided to take a closer look at VTI's specification for nImp and pImp masks. (VTI's latest spec, 02-10001, Rev *C, changed the specification for nImp, but we hadn't been following the old specification very well either.) Oversimplified, we used to bias both nImp and pImp by 1.5 microns per side, but now we bias nImp by 2.0 microns per side and pImp by 2.5 microns per side for VTI, as they seem to specify. This has the effect of providing better protection of diffusion shapes from unwanted implants, but may risk failing to implant all of the diffusion that should be implanted. (We don't yet know whether ICL can live with this biasing.) See /nimitz/cedar/users/Hoel.pa/Dragon/Foundry/- ImplantMaskIssues7Feb86.tioga for details. d. Note that we still aren't doing everything according to VTI's Tooling Specification. But we think we have the appropriate waivers from VTI. i. nWell and pWell are negotiated specially, since we want a p+ to n+ spacing of 10 microns and VTI's standard process supports 12 microns. ii. pImp is generated to protect only ndif rather than everything except pdif. We think that's good for the implanter equipment. We also think it doesn't make any difference to the chip. iii. cut2 is still made the same for ICL and VTI, at 0.5-micron resolution and no biasing. However, in the special case that the via is drawn 2 x 2 microns and overlaps diffusion, VTI asks for biasing the portion that is over diffusion by 0.25 microns per side. (That requires 0.25-micron resolution.) (Note that VTI's approach could make some non-rectangular vias on the mask plate.) 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