TestCrossRAM:
PUBLIC
PROC = {
context: CoreCompose.Context ← CoreCompose.CreateContext[];
ct: Core.CellType ← CoreCompose.CreateStructure["CrossRAM", context];
tw: Core.Wire ← CoreOps.CopyWire[ct.public];
testPort: Ports.Port;
intermediatePort: Ports.Port;
simulation: Rosemary.Simulation;
Eval: TestEvalProc = {
Ports.CopyPortValue[from: testPort, to: intermediatePort];
Rosemary.Settle[simulation];
Ports.CheckPortValue[truth: testPort, question: intermediatePort];
};
Ports.InitPort[wire: tw[Vdd], initDrive: infinite];
Ports.InitPort[wire: tw[Gnd], initDrive: infinite];
Ports.InitPort[wire: tw[PadVdd], initDrive: infinite];
Ports.InitPort[wire: tw[PadGnd], initDrive: infinite];
Ports.InitPort[wire: tw[nPrecharge], initDrive: force];
Ports.InitPort[wire: tw[Access], initDrive: force];
Ports.InitPort[wire: tw[Write], initDrive: force];
Ports.InitPort[wire: tw[Read], initDrive: force];
Ports.InitPort[wire: tw[Address], initType: c, initDrive: force];
Ports.InitPort[wire: tw[Data], initType: c, initDrive: none];
testPort ← Ports.CreatePort[tw];
intermediatePort ← Ports.CreatePort[tw];
simulation ← Rosemary.InstantiateCellType[ct, intermediatePort];
simulation ← Rosemary.InstantiateInstances[&ct, "JustAboveTransistors", intermediatePort];
Write2Read2[testPort, Eval];
};
Write2Read2:
PROC [p: Ports.Port, Eval: TestEvalProc] = {
AccessRAM:
PROC [write:
BOOL, address:
CARDINAL, data:
CARDINAL] = {
p[Address].c ← address;
precharge
p[nPrecharge].b ← FALSE;
Eval[];
p[nPrecharge].b ← TRUE;
Eval[];
enable select line
p[Access].b ← TRUE;
if write then enable write drivers
IF write
THEN {
p[Data].d ← force;
p[Write].b ← TRUE;
}
ELSE {
p[Data].d ← expect;
p[Read].b ← TRUE;
};
p[Data].c ← data;
Eval[];
disable select line
p[Access].b ← p[Write].b ← p[Read].b ← FALSE;
p[Data].d ← none;
Eval[];
};
p[Vdd].b ← TRUE; p[Gnd].b ← FALSE;
p[PadVdd].b ← TRUE; p[PadGnd].b ← FALSE;
p[nPrecharge].b ← TRUE; p[Access].b ← FALSE;
p[Write].b ← FALSE; p[Read].b ← FALSE;
Eval[! Rosemary.Stop => RESUME];
AccessRAM[write: TRUE, address: 0, data: 0];
AccessRAM[write: TRUE, address: 1, data: 0FFH];
AccessRAM[write: FALSE, address: 0, data: 0];
AccessRAM[write: FALSE, address: 1, data: 0FFH];
};