<> <> <> <> <> <> <> DIRECTORY CoreCompose, CrossRAM, Ports, Rosemary; CrossRAMImpl: CEDAR PROGRAM <> IMPORTS CoreCompose, Ports, Rosemary = BEGIN OPEN CrossRAM, CoreCompose; rowQuads: INT = 58; columnOcts: INT = 15; -- when changing this parameter, add new DataB[i] pins in the cell library. addressBits: INT = 11; dataBits: INT = columnOcts; select: INT = 8; log2Select: INT = 3; addressDecoderBits: INT = 8; AddressIndex: TYPE = [0 .. addressBits); DataIndex: TYPE = [0 .. dataBits); CrossRAM: ROPE = RegisterStructureProc[name: "CrossRAM", proc: CreateCrossRAM]; CreateCrossRAM: StructureProc = { <> PushInt[context: context, prop: $rowQuads, val: rowQuads]; PushInt[context: context, prop: $columnOcts, val: columnOcts]; PushInt[context: context, prop: $addressBits, val: addressBits]; PushInt[context: context, prop: $dataBits, val: dataBits]; PushInt[context: context, prop: $select, val: select]; PushInt[context: context, prop: $log2Select, val: log2Select]; PushInt[context: context, prop: $addressDecoderBits, val: addressDecoderBits]; cellType _ CreateRecordCell[ name: CrossRAM, context: context, public: CreateWires[context, "Vdd, Gnd, PadVdd, PadGnd, nPrecharge, Access, Write, Read, Address[seq: addressBits], Data[seq: dataBits]"], onlyInternal: CreateWires[context, "nPrechargeB, AccessB, WriteB, nWriteB, ReadB, nReadB, AddressB[seq: addressBits], DataB[seq: dataBits]"] <<,instances: LIST [>> <<[type: CreateStructure[name: CrossRAMInner, context: context]],>> <<[type: CreateStructure[name: CrossRamPadFrame, context: context]]]>> ]; Ports.InitPort[wire: cellType.public[Address], initType: c]; Ports.InitPort[wire: cellType.public[Data], initType: c]; <> <> <> <> <> <> <<[type: CreateStructure[name: CrossRAMInner, context: context]],>> <<[type: CreateStructure[name: CrossRamPadFrame, context: context]]>> <<]];>> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <<};>> <> <> Rosemary.Bind[cellType: cellType, roseClassName: CrossRAMRoseClass]; }; CrossRAMRoseClass: ROPE = Rosemary.Register[roseClassName: CrossRAM, init: CrossRAMInit, evalSimple: CrossRAMSimple]; CrossRAMInit: Rosemary.InitProc = { stateAny _ NEW[CrossRAMStateRec[4*rowQuads]]; IF dataBits>16 OR addressBits>16 THEN ERROR; }; CrossRAMSimple: Rosemary.EvalProc = { state: CrossRAMState _ NARROW[stateAny]; IF NOT p[Vdd].b OR p[Gnd].b OR NOT p[PadVdd].b OR p[PadGnd].b THEN SIGNAL Rosemary.Stop[]; IF (NOT p[nPrecharge].b AND p[Access].b) OR (p[Write].b AND p[Read].b) OR (NOT p[nPrecharge].b AND p[Write].b) THEN SIGNAL Rosemary.Stop[]; IF NOT p[nPrecharge].b THEN state.precharged _ TRUE; p[Data].d _ none; IF p[Access].b THEN { IF NOT state.precharged THEN SIGNAL Rosemary.Stop[]; IF state.accessOccured AND state.address#p[Address].c THEN SIGNAL Rosemary.Stop[]; state.accessOccured _ TRUE; state.address _ p[Address].c; IF p[Read].b THEN { p[Data].c _ state.memory[state.address].data; p[Data].d _ drive; }; IF p[Write].b THEN state.memory[state.address].data _ p[Data].c; }; IF NOT p[Access].b AND state.accessOccured THEN { state.accessOccured _ FALSE; state.precharged _ FALSE; }; }; <> <> <> <> <> <> <<[type: inputPad, actual: "Vdd: PadVdd, Gnd: PadGnd, Pad: nPrecharge, Output: nPrechargeB"],>> <<[type: inputPad, actual: "Vdd: PadVdd, Gnd: PadGnd, Pad: Access, Output: AccessB"],>> <<[type: differentialInputPad, actual: "Vdd: PadVdd, Gnd: PadGnd, Pad: Write, Output: WriteB, nOutput: nWriteB"],>> <<[type: differentialInputPad, actual: "Vdd: PadVdd, Gnd: PadGnd, Pad: Read, Output: ReadB, nOutput: nReadB"]];>> <> <> <> <> <> <> <<-- BS: changed for generating layout>> <> <> <> <> <> <> <> <> <> <> <> <> <> <<};>> <<>> <> <> <> <> <> <> <> <> <> <> <> <> <> <<[type: bottom],>> <<[type: CreateStructure[name: Middle, context: context], actual: "VddMiddle: Vdd, GndLeft: Gnd, GndMiddle: Gnd, VddArray: Vdd, GndArray: Gnd"],>> <<[type: CreateStructure[name: "CrossRAMTop", context: context], actual: "VddLeft: Vdd, VddRight: Vdd"]]];>> <> <> <<};>> <<>> <> <> <> <> <> <> <> <> <> <> <> <<[type: CreateStructure[name: "Decoder", context: context], actual: "VddRight: VddArray"],>> <<[type: CreateStructure[name: "RAMArray", context: context], actual: IO.PutFR["Gnd: GndArray, Vdd: [%g]", IO.rope[nRopes]]],>> <<[type: CreateStructure[name: RightPowerSeq, context: context], actual: "Vdd: VddArray"]>> <<]];>> <> <> <<};>> <<>> <> <> <> <> <> <> <> <> <> <<};>> <<>> <> <> <> <> <> <> <> <> <<};>> RegisterIntProperty[prop: $rowQuads]; RegisterIntProperty[prop: $columnOcts]; RegisterIntProperty[prop: $addressBits]; RegisterIntProperty[prop: $dataBits]; RegisterIntProperty[prop: $select]; RegisterIntProperty[prop: $log2Select]; RegisterIntProperty[prop: $addressDecoderBits]; END.