
    <<CrossRAMBottom.mesa>>
        <<Copyright © 1985 by Xerox Corporation.  All rights reserved.>>
        <<Barth, November 7, 1985 4:44:40 pm PST>>
        <<Louis Monier October 23, 1985 4:50:52 pm PDT>>
        <<Bertrand Serlet December 6, 1985 2:07:11 pm PST>>
        <<>>
    DIRECTORY Core, CoreCompose, CoreFlatten, CoreProperties, PWCore, Rosemary, Sinix;

    CrossRAMBottom: CEDAR PROGRAM
        IMPORTS CoreCompose, CoreFlatten, CoreProperties, PWCore, Rosemary, Sinix = 
        BEGIN OPEN CoreCompose;

    <<columnOcts, addressDecoderBits: INT>>
    Bottom: ROPE = RegisterStructureProc[name: "Bottom", proc: CreateBottom];
        CreateBottom: StructureProc = {
            cellType _ CreateRecordCell[
                name: Bottom,
                context: context,
                public: CreateWires[context, "Vdd, nPrechargeB, AccessB, Bit[SEQ:8*columnOcts], nBit[SEQ:8*columnOcts]"],
                instances: LIST [
                    [type: CreateStructure[name: "BottomDecoderLeft", context: context]],
                    [type: CreateStructure[name: "DecoderSeq", context: context]],
                    [type: CreateStructure[name: "BottomDecoderRight", context: context]],
                    [type: CreateStructure[name: "Precharge", context: context]],
                    [type: CreateStructure[name: "BottomRight", context: context]]]];
            IF GetBool[context, $PWCore] THEN PWCore.SetAbutX[cellType: cellType];
            IF GetBool[context, $Sinix] THEN [] _ Sinix.Extract[PWCore.GetLayout[cellType]];
            };

    BottomDecoderLeft: ROPE = RegisterStructureProc[name: "BottomDecoderLeft", proc: CreateBottomDecoderLeft];
        CreateBottomDecoderLeft: StructureProc = {
            cellType _ CreateRecordCell[
                name: BottomDecoderLeft,
                context: context,
                public: CreateWires[context, "Vdd"]];
            IF GetBool[context, $PWCore] THEN PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
            IF GetBool[context, $Sinix] THEN [] _ Sinix.Extract[PWCore.GetLayout[cellType]];
            };

<<Ports: Vdd>>
    DecoderSeq: ROPE = RegisterStructureProc[name: "DecoderSeq", proc: CreateDecoderSeq];
        CreateDecoderSeq: StructureProc = {
            cellType _ CreateSequenceCell[
                name: DecoderSeq,
                baseCell: CreateStructure[name: "BottomDecoder", context: context],
                count: GetInt[context: context, prop: $addressDecoderBits]];
            IF GetBool[context, $PWCore] THEN PWCore.SetArrayX[cellType: cellType];
            IF GetBool[context, $Sinix] THEN [] _ Sinix.Extract[PWCore.GetLayout[cellType]];
            };

    BottomDecoder: ROPE = RegisterStructureProc[name: "BottomDecoder", proc: CreateBottomDecoder];
        CreateBottomDecoder: StructureProc = {
            cellType _ CreateRecordCell[
                name: BottomDecoder,
                context: context,
                public: CreateWires[context, "Vdd"]];
            IF GetBool[context, $PWCore] THEN PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
            IF GetBool[context, $Sinix] THEN [] _ Sinix.Extract[PWCore.GetLayout[cellType]];
            };

    BottomDecoderRight: ROPE = RegisterStructureProc[name: "BottomDecoderRight", proc: CreateBottomDecoderRight];
        CreateBottomDecoderRight: StructureProc = {
            cellType _ CreateRecordCell[
                name: BottomDecoderRight,
                context: context,
                public: CreateWires[context, "Vdd, nPrechargeB, AccessB"]];
            IF GetBool[context, $PWCore] THEN PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
            IF GetBool[context, $Sinix] THEN [] _ Sinix.Extract[PWCore.GetLayout[cellType]];
            };

<<Ports: Vdd, nPrechargeB1, nPrechargeB2, Bit[0..8*columnOcts), nBit[0..8*columnOcts)>>
    Precharge: ROPE = RegisterStructureProc[name: "Precharge", proc: CreatePrecharge];
        CreatePrecharge: StructureProc = {
            cellType _ CreateSequenceCell[
                name: Precharge,
                baseCell: CreateStructure[name: PrechargeOctStitch, context: context],
                count: GetInt[context: context, prop: $columnOcts],
                sequencePorts: "Bit, nBit"];
            IF GetBool[context, $PWCore] THEN PWCore.SetArrayX[cellType: cellType];
            IF GetBool[context, $Sinix] THEN [] _ Sinix.Extract[PWCore.GetLayout[cellType]];
            };

    PrechargeOctStitch: ROPE = RegisterStructureProc[name: "PrechargeOctStitch", proc: CreatePrechargeOctStitch];
        CreatePrechargeOctStitch: StructureProc = {
            cellType _ CreateRecordCell[
                name: PrechargeOctStitch,
                context: context,
                public: CreateWires[context, "Vdd, nPrechargeB, Bit[SEQ:8], nBit[SEQ:8]"],
                instances: LIST [
                    [type: CreateStructure[name: "PrechargeOct", context: context]],
                    [actual: "VddWell: Vdd, nPrechargeB1: nPrechargeB, nPrechargeB2: nPrechargeB", 
                        type: CreateStructure[name: "PrechargeStich", context: context]]
                    ]];
            IF GetBool[context, $PWCore] THEN PWCore.SetAbutX[cellType: cellType];
            IF GetBool[context, $Sinix] THEN [] _ Sinix.Extract[PWCore.GetLayout[cellType]];
            };

<<Ports: Vdd, nPrechargeB1, nPrechargeB2, Bit[0..8), nBit[0..8)>>
    PrechargeOct: ROPE = RegisterStructureProc[name: "PrechargeOct", proc: CreatePrechargeOct];
        CreatePrechargeOct: StructureProc = {
            cellType _ CreateSequenceCell[
                name: PrechargeOct,
                baseCell: CreateStructure[name: "PrechargeSlice", context: context],
                count: 8,
                sequencePorts: "Bit, nBit"];
            IF GetBool[context, $PWCore] THEN PWCore.SetArrayX[cellType: cellType];
            IF GetBool[context, $Sinix] THEN [] _ Sinix.Extract[PWCore.GetLayout[cellType]];
            };

    PrechargeSlice: ROPE _ RegisterStructureProc[name: "PrechargeSlice", proc: CreatePrechargeSlice];
        CreatePrechargeSlice: StructureProc = {
            peTranType: Core.CellType _ CreateTransistor[name: "Transistor", type: pE];
            cellType _ CreateRecordCell[
                name: PrechargeSlice,
                context: context,
                public: CreateWires[context, "Vdd, nPrechargeB, Bit, nBit"],
                instances: LIST [
                    [actual: "gate: nPrechargeB, ch1: Bit, ch2: Vdd",
                        type: peTranType],
                    [actual: "gate: nPrechargeB, ch1: nBit, ch2: Vdd",
                        type: peTranType]]];
            IF GetBool[context, $PWCore] THEN PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
            IF GetBool[context, $Sinix] THEN [] _ Sinix.Extract[PWCore.GetLayout[cellType]];
            IF GetBool[context, $Rosemary] THEN Rosemary.Bind[cellType: cellType, roseClassName: PrechargeSliceRoseClass];
            CoreProperties.PutCellTypeProp[on: cellType, prop: CoreFlatten.CoreFlattenCutSets, value: LIST["JustAboveTransistors"]];
            };
        PrechargeSliceRoseClass: ROPE = Rosemary.Register[roseClassName: PrechargeSlice, init: PrechargeInit, evalSimple: PrechargeSimple];
        Vdd: NAT = 0;
        nPrechargeB: NAT = 1;
        Bit: NAT = 2;
        nBit: NAT = 3;
        PrechargeInit: Rosemary.InitProc = {
            FOR port: NAT IN [0..p.size) DO
                p[port].type _ b;
                ENDLOOP;
            };
        PrechargeSimple: Rosemary.EvalProc = {
            IF NOT p[Vdd].b THEN SIGNAL Rosemary.Stop[];
            p[nBit].d _ p[Bit].d _ IF NOT p[nPrechargeB].b THEN drive ELSE none;
            p[nBit].b _ p[Bit].b _ TRUE;
            };

    PrechargeStich: ROPE = RegisterStructureProc[name: "PrechargeStich", proc: CreatePrechargeStitch];
        CreatePrechargeStitch: StructureProc = {
            cellType _ CreateRecordCell[
                name: PrechargeStich,
                context: context,
                public: CreateWires[context, "Vdd, VddWell, nPrechargeB1, nPrechargeB2"]];
            IF GetBool[context, $PWCore] THEN PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
            IF GetBool[context, $Sinix] THEN [] _ Sinix.Extract[PWCore.GetLayout[cellType]];
            };

    BottomRight: ROPE = RegisterStructureProc[name: "BottomRight", proc: CreateBottomRight];
        CreateBottomRight: StructureProc = {
            cellType _ CreateRecordCell[
                name: BottomRight,
                context: context,
                public: CreateWires[context, "Vdd"]];
            IF GetBool[context, $PWCore] THEN PWCore.SetGet[cellType: cellType, source: NARROW[GetRef[context, $sourceCDDesign]]];
            IF GetBool[context, $Sinix] THEN [] _ Sinix.Extract[PWCore.GetLayout[cellType]];
            };

    END.