As a result of understanding why chips from run MPC5NA did not work, I found misaligned metal2 connections between some DecoderLogic cells and their associated SRamTwoBits or DRamTwoBits cells. The misalignments were by 0.5 lambda. (They caused design rule violations, but were not believed to be contributing materially to observed problems.) The problem was not exactly with the CrossRAMCellLibrary but with the fact that the patchwork/core sofetware flipped some cells during assembly, and the cells were not designed to be flipped. (In particular the software made cells DecoderLogic@125 and -noname-@2217 from the library's DecoderLogic cell, flipping the latter.) The fix was to edit one of these cells (-noname-@2217, I think) to make the connections match. This was aesthetically undesirable, but it minimimized the extent of the required changes. In the long run, it is recommended that the cells not be flipped.
Found: ?
Fixed: February 4, 1986, in:
CrossRAM03Fabricated4Feb86 ONLY. (Not fixed in CrossRAMCellLibrary. In fact, not fixable in CrossRAMCellLibrary, without rethinking the design, since the problem was with the interaction between the library and the core stuff.)