CrossRAM03MPC5NSFabProblem.tioga
Hoel, February 3, 1986 7:20:57 pm PST
Problem with Fabrication of CrossRAM03
on MPC5NS
Introduction
Symptoms
Jim Gasbarro looked at some CrossRAM03 chips. First on Friday, January 24th. Next on Thursday, January 30th (?).
Standard CrossRAM Test
The chips Jim looked at failed the standard test completely. No good bits.
What works
I believe Jim said the following things work:
o Pads
o Address decoder.
Word Line
Jim says the word lines seem to be stuck at 2.5 volts or so. All of them. Jim took a look at the CrossRAMCellLibrary (from my disk) and couldn't see anything wrong with the circuitry that drives the word lines.
VDD Bus
Jim also noticed that the VDD bus on the right side of the chip is carrying lots of current! The voltage at the top is noticeably lower than the voltage at the bottom. (More than a volt, I think he said.) However, the chip as a whole is drawing only about 100 microAmps (I think he said).
Layout
DecoderLogic Cell Flip
Inspection of the layout reveals that there is a mismatch at the interface of the DecoderLogic and DRamTwoBits cells, and also at the interface of the DecoderLogic and SRamTwoBits cells.
Closer inspection reveals the causes:
1. The VDD bus width of the DecoderLogic cell is 11 lambda, while the VDD bus width of the *RamTwoBits cells is 11.5 lambda. This lacks grace, but is OK functionally. (It ought to be fixed, just for aesthetics.)
2. All DRamTwoBits and SRamTwoBits cells are the same orientation, but every other DecoderLogic cell is mirrored vertically. Since the DecoderLogic, DRamTwoBits, and SRamTwoBits cells are not symmetric vertically, interfacing a flipped DecoderLogic cell with a non-flipped *RamTwoBits cell results in a mismatch of 0.5 lambda. This results in some metal2 width violations (3.5 lambda) and some metal2 spacing violations (3.5 lambda). But these were not caught by Spinifex because the chip was too large and Spinifex died before finishing the check. (I wonder why the son-of-patchwork code was written to flip the DecoderLogic cells.)
This error might explain decreased yield, but it doesn't explain zero yield.
DecoderLogicHalf Cell: Shorted Transistor
Jim Gasbarro found this one. There is an extra split contact placed on the p-channel word line driver's drain, shorting it to VDD. This explains why the word line drivers were being pulled high. It also explains why the interior of the chip was drawing so much current, since the complementary n-channel word line drivers are supposed to be on nearly always.
Fixes To Layout
Generally
I think it would be a good idea to try to make all fixes without rerunning core, i.e., by editing the leaf cells with Chipndale.
DecoderLogic Cell Flip
The fix is to edit cells DecoderLogic@125 and -noname-@2217 (which were made by core-patchwork from cell DecoderLogic) to match metal2 lines to the *RamTwoBits cells.
1. -noname-@2217: made the VDD bus 1/2 micron wider.
2. DecoderLogic@125: made the VDD bus 1/2 micron wider. Also moved VDD and word lines up 1/2 micron. (I did this rather than flipping the cell, because the core-patchwork also flipped many mating cells and I didn't want to unflip them all.)
Only the metal2 mask need be affected. It would cost perhaps $1500.
We could consider omitting this fix. VTI's metal2 width design rule is 3 lambda, so the 3.5 lambda wide traces should be OK. However, VTI's metal2 spacing design rule is 4 lambda, so the 3.5 lambda wide spaces would be cheating.
DecoderLogicHalf Cell: Shorted Transistor
The fix is to remove the unwanted split contact. That alters the cut, thin ox, n+ implant, and p+ implant masks.
For the purpose of saving money on the proposed VTI run, the following plan can be considered for minimizing the number of masks actually changed:
1. The cut mask must be redone, at a cost of perhaps $1500.
2. The thin ox mask can be fixed "for free," since is must be remade in any case to meet the VTI mask biasing requirements. It is possible to draw p+ diffusion 1.5 microns to the right (i.e., retreated from the split contact's n+/p+ edge) so that all the thin ox is covered by p+ implant by the required 1.5 microns. In this case, neither implant mask need be redone. If this were done, the mask set used to fabricate the chip would not correspond to any Chipndale source layout. Is this OK?
Anyhow, I made the following changes to cell DecoderLogicHalf:
1. Removed the unwanted split contact.
2. Moved the left edge of the p+ diffusion for two transistors and one center stripe 1.5 microns to the right. (This is the hack that permits us not to remake the implant masks. It needn't and probably shouldn't be done to the CrossRAMCellLibrary for future CrossRAMs.)
Design Rule Checking
Theory
At the Dragon Meeting of February 3, 1986, I got an idea of some more things to try, to allow Spinifex to complete the design rule check without running out of VM.
1. Start with more VM. (One can ask for up to 64K pages; the default is 25K pages.) Also, to minimize thrashing, use a machine with 8K words of real memory, not 4K.
2. Don't check all the chip. For example, check only the interior and not the pad frame or onion routing. Giordano points out that Spinifex gets especially bogged down in checking the latter cells, because bounding box checking doesn't eliminate any more detailed checking.
Practice
First, I tried checking only part of the chip, on Nimitz, without getting more VM.
1. Cell -noname-@****: three levels up from DecoderLogic@125, I think: no errors (other than the 2 x 2 via cell).
2. Cell -noname-@1937: I think this is the entire interior.