CrossRAM03AExplanation.tioga
Hoel, May 4, 1987 12:31:21 pm PDT
Hoel, May 3, 1987 1:19:28 pm PDT
Explanation for CrossRAM03A.df
1. Introduction
Some time ago, the CrossRAM03 design, as kept in CrossRAM3.df, fell into disrepair because the layout generation software failed to track changes in the DATools. Later, Rick Barth repaired everything and put the resulting design into CrossRAM4.df
However, for the November 1986 foundry run, CrossRAM04 did not yet exist, so I decided to edit the ChipNDale (object) file to accomplish the required conversion from CMosA to CMosB technology and to clean up a few design rule violations. Later, for the May 1987 foundry run, I decided to edit the ChipNDale (object) file to accomplish the required conversion from ChipNDale23 format to ChipNDale24 format, and to clean up a few design rule violations. In both cases, there were no "real" design changes to CrossRAM03.
Philosophically, one can argue that it is bad form to edit object files this way, but I claim it was a justifiable expedient.
The purpose of CrossRAM03A.df is to keep track of these edits to the ChipNDale layout of CrossRAM03, rather than filing them under CrossRAM3.df.
2. Files
2.1. CrossRAM03Fabricated4Feb86CMosB.dale
This file was made by editing CrossRAM03Fabricated4Feb86.dale (from CrossRAM3.df), converting it from CMosA to CMosB technology. It is in ChipNDale23 format.
An attempt was made to fix minor design rule errors, such as nwell surround n+ by 4 lambda and nwell spacing of 10 lambda. But, due to the structure of the design, this proved too difficult to finish in the timeframe available. So the file has some error rectangles embedded in it. (The layout generation software chose to make lots of DecoderZero@<number> cells, all alike, rather than just use the DecoderZero cell in the cell library. Same for DecoderOne.)
2.2. CrossRAM03Fabricated1May87A.dale
This file was made by editing CrossRAM03Fabricated4Feb86CMosB.dale (see Section 2.1.). It was converted from ChipNDale23 format to ChipNDale24 format by reading it into ChipNDale24.
(The conversion discovered a bug in ChipNDale24 which caused a cell with an interest rectangle larger than its bounding box and an error rectangle outside its bounding box to be translated to the wrong position. Christian fixed the bug in my local copy of Chipndale24; we think no new bugs were introduced.)
I also cleaned up the design structure by replacing references to DecoderZero@<number> with references to DecoderZero and similarly for DecoderOne and DecoderLeft. Then I fixed the nwell design rule violations attributable to these cells.
Note that this version of the CrossRAM03 should now follow the Dragon CMOS Design Rules. However, we haven't actually done a comprehensive DRC of the design lately. Anyhow, as of March 13, 1987, the Dragon project decided to adopt the VTI Design Rules, at least for new designs. Eventually, it might be nice to have a CrossRAM that follows the VTI rules, but I decided that it would be too painful to do that for the May 1987 foundry run. Here's what would have to be done:
o To observe the more conservative rule about spacing between p+ and n+ across a well boundary, the number of rows would have to be decreased.
o To avoid the use of angle transistors, new memory cells would have to be used; this would likely decrease the number of rows and increase the number of columns. (Angle transistors aren't explicitly forbidden in VTI's rules, but VTI says over the phone that they'd rather not see them, especially for the 1.6-micron process.)
o It would be possible to use the more aggressive rules about metal1 and metal2 widths, but it would not be mandatory. (On the other hand, if design rule minimum dimensions are not extensively used, one can argue that the CrossRAM is not a good test.)
o The test software has to be changed to track the layout changes.
Clearly, the switch to VTI rules should be done (if at all) in the context of CrossRAM04, so that we can take advantage of layout generation software that works.
2.3. CrossRAM03AExplanation.tioga
This the file you're now reading.
2.4. CrossRAM03A.df