DIRECTORY
Basics, BitmapViewer, Commander, CRIO, ImagerPixelMap, ICTest, IO, Process, Rope, ViewerClasses, ViewerOps;

CRTest: CEDAR PROGRAM 
IMPORTS Basics, BitmapViewer, Commander, CRIO, ImagerPixelMap, ICTest, IO, Process, ViewerOps =

BEGIN
Address: TYPE = [0..2048);
size: INT;
DataIndex: TYPE = [0..32);

LastRow: INT = 255;
LastColumn: INT = 255;
rectangle: ImagerPixelMap.DeviceRectangle = [0, 0, LastRow+1, LastColumn+1];
dataViewer: ViewerClasses.Viewer;
dataBitmap: ImagerPixelMap.PixelMap;
errorViewer: ViewerClasses.Viewer;
errorBitmap: ImagerPixelMap.PixelMap;

Viewer: TYPE = ViewerClasses.Viewer;
ROPE: TYPE = Rope.ROPE;
errorBitMap: ROPE _ "CrossRAM Error Bit Map";
dataBitMap: ROPE _ "CrossRAM Data Bit Map";

cr02: BOOL _ FALSE;
cr03: BOOL _ FALSE;
dataDisplay: BOOL _ FALSE;
noRefresh: BOOL _ FALSE;

bigChip: BOOL _ FALSE;

Ram: TYPE = ARRAY [0..2048) OF LONG CARDINAL;
ram: REF Ram;

h: ICTest.Handle _ NIL;

Init: PROC RETURNS [ok: BOOL] = {
IF (cr02 AND cr03) OR (NOT cr02 AND NOT cr03) THEN {
IO.PutF[h.viewerout, "Select one chip type\n"];
RETURN[FALSE];
};
size _ SELECT TRUE FROM
cr02 => 1920, -- 60*4*8 --
cr03 => 1856, -- 58*4*8 --
ENDCASE => 0;
IF dataDisplay AND (dataViewer _ ViewerOps.FindViewer[dataBitMap]) = NIL THEN {
dataViewer _ BitmapViewer.Create[info: [name: dataBitMap]];
dataBitmap _ ImagerPixelMap.Create[0, rectangle];
BitmapViewer.SetBitmap[dataViewer, dataBitmap];
ImagerPixelMap.Clear[dataBitmap];
};
IF (errorViewer _ ViewerOps.FindViewer[errorBitMap]) = NIL THEN {
errorViewer _ BitmapViewer.Create[info: [name: errorBitMap]];
errorBitmap _ ImagerPixelMap.Create[0, rectangle];
BitmapViewer.SetBitmap[errorViewer, errorBitmap];
};
ImagerPixelMap.Clear[errorBitmap];
IF NOT h.enableTester AND ram=NIL THEN ram _ NEW[Ram];
IF errorViewer.iconic THEN ViewerOps.OpenIcon[icon: errorViewer];
ViewerOps.ChangeColumn[viewer: errorViewer, newColumn: left];
ViewerOps.BottomViewer[viewer: errorViewer];
RETURN[TRUE];
};

NoRefresh: ICTest.ControlProc = {
noRefresh _ control;
};

TesterOn: PROC [] = {
IF h.enableTester THEN {
CRIO.Init[bigChip: bigChip];
CRIO.EmergencyRefresh[on: NOT noRefresh];
CRIO.Test[on: TRUE];
Process.Pause[Process.MsecToTicks[500]];
} ;
};

TesterOff: PROC [] = {
IF h.enableTester THEN {
CRIO.Test[on: FALSE];
Process.Pause[Process.MsecToTicks[500]];
};
};

DataDisplay: ICTest.ControlProc = {
dataDisplay _ control;
};

CrossRAM02: ICTest.ControlProc = {
cr02 _ control;
};

CrossRAM03: ICTest.ControlProc = {
cr03 _ control;
};

SimpleTest: ICTest.TestProc = {
IF NOT Init[] THEN RETURN;
TesterOn[];
FOR i: INT IN [0..size) DO 
CycleRAM[i, 0, TRUE];
CycleRAM[i, 0, FALSE];
CycleRAM[i, 0FFFFFFFFh, TRUE];
CycleRAM[i, 0FFFFFFFFh, FALSE];
ICTest.CheckStop[h];
ENDLOOP;
Refresh[];
TesterOff[];
};

LoopTest: ICTest.TestProc = {
Loop: PROC [] = {
DO 
CycleRAM[02AAH, 0AAAAAAAAH, TRUE];
CycleRAM[0555H, 55555555H, TRUE];
CycleRAM[02AAH, 0AAAAAAAAH, FALSE];
CycleRAM[0555H, 55555555H, FALSE];
ICTest.CheckStop[h];
ENDLOOP;
};
IF NOT Init[] THEN RETURN;
TesterOn[];
Loop[! ICTest.AbortDieSignal => TesterOff[]];
TesterOff[];
};

AddressTest: ICTest.TestProc = {
IF NOT Init[] THEN RETURN;
TesterOn[];
FOR i: INT IN [0..size) DO 
CycleRAM[i, i, TRUE];
ICTest.CheckStop[h];
ENDLOOP;
Refresh[];
FOR i: INT IN [0..size) DO 
CycleRAM[i, i, FALSE];
ICTest.CheckStop[h];
ENDLOOP;
Refresh[];
TesterOff[];
};

IllinoisTest: ICTest.TestProc = {
StepIndex: TYPE = [0..8);
complementUpper: ARRAY StepIndex OF BOOL = [TRUE,TRUE,FALSE,TRUE,FALSE,FALSE,TRUE,FALSE];
writeData: ARRAY StepIndex OF BOOL = [TRUE,FALSE,TRUE,TRUE,FALSE,TRUE,FALSE,FALSE];
readData: ARRAY StepIndex OF BOOL = [FALSE,FALSE,FALSE,TRUE,TRUE,TRUE,TRUE,FALSE];
halfBit: INT _ LAST[Address]+1;
IF NOT Init[] THEN RETURN;
TesterOn[];
FOR address: INT IN [0..size) DO
CycleRAM[address, 0, TRUE];
ENDLOOP;
UNTIL (halfBit _ halfBit/2) = 4 DO
FOR step: StepIndex IN StepIndex DO
HalfStep[upper: complementUpper[step], data: writeData[step], write: TRUE, halfbit: halfBit];
HalfStep[upper: NOT complementUpper[step], data: readData[step], write: FALSE, halfbit: halfBit];
Refresh[];
ICTest.CheckStop[h];
ENDLOOP;
ENDLOOP;
TesterOff[];
};

HalfStep: PROC [upper: BOOL, data: BOOL, write: BOOL, halfbit: INT] = {
address: CARDINAL _ IF upper THEN halfbit ELSE 0;
addressMod: CARDINAL;
DO
CycleRAM[address, IF data THEN 0FFFFFFFFH ELSE 0, write];
address _ address + 1;
addressMod _ address MOD (2*halfbit);
IF (upper AND addressMod=0) OR (NOT upper AND addressMod=halfbit) THEN address _ address + halfbit;
IF address>=size THEN EXIT;
ENDLOOP;
};

CycleRAM: PROC [address: Address, data: LONG CARDINAL, write: BOOL] = {
ramAdd: Address;
SELECT TRUE FROM
cr02 => {
address _ address + 128;
ramAdd _ address;
};
cr03 => {
address _ address + 192;
ramAdd _ Basics.BITAND[address, 07h];
ramAdd _ Basics.BITOR[ramAdd, IF Basics.BITAND[address, 100h]#0 THEN 008h ELSE 0];
ramAdd _ Basics.BITOR[ramAdd, IF Basics.BITAND[address, 200h]#0 THEN 010h ELSE 0];
ramAdd _ Basics.BITOR[ramAdd, IF Basics.BITAND[address, 040h]#0 THEN 020h ELSE 0];
ramAdd _ Basics.BITOR[ramAdd, IF Basics.BITAND[address, 080h]#0 THEN 040h ELSE 0];
ramAdd _ Basics.BITOR[ramAdd, IF Basics.BITAND[address, 010h]#0 THEN 080h ELSE 0];
ramAdd _ Basics.BITOR[ramAdd, IF Basics.BITAND[address, 020h]#0 THEN 100h ELSE 0];
ramAdd _ Basics.BITOR[ramAdd, IF Basics.BITAND[address, 400h]#0 THEN 200h ELSE 0];
ramAdd _ Basics.BITOR[ramAdd, IF Basics.BITAND[address, 008h]#0 THEN 400h ELSE 0];
ramAdd _ Basics.BITXOR[ramAdd, 7f0h];
};
ENDCASE => ERROR;
IF write THEN {
word: CARDINAL;
IF h.enableTester THEN CRIO.CRWrite[ramAdd, data] ELSE ram[address] _ data;
IF dataDisplay THEN {
word _ Basics.HighHalf[data];
IF bigChip THEN FOR bit: CARDINAL IN [0..16) DO
PutBit[dataBitmap, address, bit, Basics.BITAND[word, 8000H] # 0];
word _ word*2;
ENDLOOP;
word _ Basics.LowHalf[data];
FOR bit: CARDINAL IN [IF bigChip THEN 0 ELSE 1..16) DO
PutBit[dataBitmap, address, bit+16, Basics.BITAND[word, IF bigChip THEN 8000H ELSE 4000H] # 0];
word _ word*2;
ENDLOOP;
};
}
ELSE {
readData: LONG CARDINAL _ data;
word: CARDINAL;
IF h.enableTester THEN readData _ CRIO.CRRead[ramAdd] ELSE readData _ ram[address];
IF readData#data THEN {
word _ Basics.BITXOR[Basics.HighHalf[readData], Basics.HighHalf[data]];
IF bigChip THEN FOR bit: CARDINAL IN [0..16) DO
IF Basics.BITAND[word, 8000H] # 0 THEN PutBit[errorBitmap, address, bit, TRUE];
word _ word*2;
ENDLOOP;
word _ Basics.BITXOR[Basics.LowHalf[readData], Basics.LowHalf[data]];
FOR bit: CARDINAL IN [IF bigChip THEN 0 ELSE 1..16) DO
IF Basics.BITAND[word, 8000H] # 0 THEN PutBit[errorBitmap, address, bit+16, TRUE];
word _ word*2;
ENDLOOP;
};
};
};

PutBit: PROC [bitmap: ImagerPixelMap.PixelMap, address: Address, bit: DataIndex, data: BOOL] = {
slow: INTEGER _ LastRow - (address/8);
fast: INTEGER _ LastColumn - (bit*8 + 7 - (address MOD 8));
PutPixel[pm: bitmap, s: slow, f: fast, val: LOOPHOLE[data, CARDINAL]];
};

Seq0: TYPE = RECORD[PACKED SEQUENCE COMPUTED CARDINAL OF [0..2)];
PixelMap: TYPE = ImagerPixelMap.PixelMap;
PutPixel: PROC [pm: PixelMap, s, f: INTEGER, val: CARDINAL] = TRUSTED INLINE {
bounds: ImagerPixelMap.DeviceRectangle _ [pm.sOrigin+pm.sMin, pm.fOrigin+pm.fMin, pm.sSize, pm.fSize];
sCheck: NAT _ bounds.sSize-1-NAT[s-bounds.sMin];
fCheck: NAT _ bounds.fSize-1-NAT[f-bounds.fMin];
line: LONG POINTER = pm.refRep.pointer + Basics.LongMult[(s - pm.sOrigin), pm.refRep.rast];
zero: [0..0] = pm.refRep.lgBitsPerPixel;
LOOPHOLE[line, LONG POINTER TO Seq0][f-pm.fOrigin]_val;
};

Refresh: PROC = {
IF dataDisplay THEN BitmapViewer.TouchUp[dataViewer, rectangle];
BitmapViewer.TouchUp[errorViewer, rectangle];
};

MakeCRTestTool: Commander.CommandProc = {
h _ ICTest.MakeICTestTool["Testing CrossRAM", 5];
ICTest.PutUpTestButton["Illinois Test", IllinoisTest, h];
ICTest.PutUpTestButton["Simple Test", SimpleTest, h];
ICTest.PutUpTestButton["Loop Test", LoopTest, h];
ICTest.PutUpTestButton["Address Test", AddressTest, h];
ICTest.PutUpControlButton["CrossRAM02", CrossRAM02, h, TRUE];
ICTest.PutUpControlButton["CrossRAM03", CrossRAM03, h, FALSE];
ICTest.PutUpControlButton["Data Display", DataDisplay, h, FALSE];
ICTest.PutUpControlButton["No Refresh", NoRefresh, h, FALSE];
};

Commander.Register[key: "///Commands/CRTest", proc: MakeCRTestTool,
doc: "Create a tool for testing CrossRAMs" ];

END.
���
¢��CRTest.mesa
Copyright c 1985 by Xerox Corporation.  All rights reserved.
Last Edited by: Gasbarro April 23, 1986 10:33:40 am PST
Gunther, November 4, 1985 3:27:24 pm PST
Barth, September 27, 1985 5:28:19 pm PDT
write zero to all locations
divide RAM by columns instead of rows
the low order bits address left to right
the high order bits address from top to bottom
the data bits are in order from right to left
�ÊH��˜�
codeš
œ™Kšœ
Ïm
œ1™<K™7K™(K™(—K˜�š
Ïk	˜	Jšœ!žœžœ*˜kK˜�—šœžœ
žœ
˜Kšžœ"žœžœ˜_—K˜�Kš
ž˜Kšœ	žœ
˜Kšœžœ
˜
Kšœžœ˜K˜�Jšœ	žœ˜Jšœžœ˜Jš
œL˜LJš
œ!˜!Jš
œ$˜$Jš
œ"˜"Jš
œ%˜%J˜�Kšœžœ˜$Kšžœžœžœ
˜Kšœ
žœ˜-Kšœžœ˜+K˜�Kšœžœžœ
˜Kšœžœžœ
˜Kšœ
žœžœ
˜Kšœžœžœ
˜K˜�Kšœ	žœžœ
˜K˜�Kšœžœžœžœ
žœ
žœ
˜-Kšœžœ˜
K˜�Kšœžœ
˜J˜�šÏnœžœžœ˜!šžœžœžœžœžœ
žœžœ˜4Kšžœ-˜/Kšžœ
žœ˜K˜—šœžœ
žœ
ž˜Kš
œ˜Kš
œ˜Kšžœ˜
—šžœ
žœ3žœ
žœ˜OJš
œ;˜;Jš
œ1˜1Jš
œ/˜/Jš
œ!˜!J˜—šžœ5žœ
žœ˜AJš
œ=˜=Jš
œ2˜2Jš
œ1˜1K˜—Jš
œ"˜"Jšžœ
žœžœžœ
žœžœ˜6Kšžœžœ'˜AKš
œ=˜=Kš
œ,˜,Kšžœ
žœ˜
Kš
œ˜K˜�—šŸ	œ˜!Kš
œ˜K˜K˜�—šŸœžœ˜šžœžœ˜Jšžœ˜Jšžœžœ˜)Jšžœ
žœ˜Jš
œ(˜(Jš
œ˜—K˜K˜�—šŸ	œžœ˜šžœžœ˜Jšžœ
žœ˜Jš
œ(˜(Jš
œ˜—K˜K˜�—šŸœ˜#Kš
œ˜K˜K˜�—šŸ
œ˜"Kš
œ˜K˜K˜�—šŸ
œ˜"Kš
œ˜K˜K˜�—šŸ
œ˜Jšžœ
žœžœ
žœ
˜Jš
œ˜šžœžœ
žœžœ
˜Jšœžœ˜Jšœžœ˜Jšœžœ˜Jšœžœ˜Jš
œ˜Jšžœ
˜—Jš
œ
˜
Jš
œ˜Jš
œ˜J˜�—šŸœ˜šŸœžœ˜šžœ
˜Jšœžœ˜"Jšœžœ˜!Jšœžœ˜#Jšœžœ˜"Jš
œ˜Jšžœ
˜Jš
œ˜——Jšžœ
žœžœ
žœ
˜Jš
œ˜Jš
œ-˜-Jš
œ˜Jš
œ˜J˜�—šŸœ˜ Jšžœ
žœžœ
žœ
˜Jš
œ˜šžœžœ
žœžœ
˜Jšœžœ˜Jš
œ˜Jšžœ
˜—Jš
œ
˜
šžœžœ
žœžœ
˜Jšœžœ˜Jš
œ˜Jšžœ
˜—Jš
œ
˜
Jš
œ˜Jš
œ˜J˜�—šŸœ˜!Kšœžœ
˜Kšœžœžœ
žœžœ
žœ
žœ
žœ
žœ
žœ
žœ
žœ˜YKšœžœžœ
žœžœ
žœ
žœ
žœ
žœ
žœ
žœ
žœ˜SKšœ
žœžœ
žœžœ
žœ
žœ
žœ
žœ
žœ
žœ
žœ˜RKšœ	žœžœ˜Jšžœ
žœžœ
žœ
˜Jš
œ˜K™K™%šžœ
žœ
žœž˜ Kšœžœ˜Kšžœ
˜—šžœž˜"šžœžœž˜#KšœEžœ˜]Kšœžœ5žœ˜aKš
œ
˜
Jš
œ˜Kšžœ
˜—Kšžœ
˜—Jš
œ˜K˜K˜�—šŸœžœ	žœžœ	žœžœ˜GKš	œ	žœžœžœ	žœ˜1Kšœžœ
˜š
ž˜Kšœžœžœžœ˜9Kš
œ˜Kšœžœ
˜%Kšžœžœžœžœžœžœ˜cKšžœžœ
žœ
˜Kšžœ
˜—K˜K˜�—š
Ÿœžœžœ
žœ	žœ˜GKš
œ˜šžœ
žœ
ž˜˜	Kš
œ˜Kš
œ˜K˜—š
œ	˜	Kš
œ˜Kšœžœ˜%Kšœžœ	žœžœžœžœ˜RKšœžœ	žœžœžœžœ˜RKšœžœ	žœžœžœžœ˜RKšœžœ	žœžœžœžœ˜RKšœžœ	žœžœžœžœ˜RKšœžœ	žœžœžœžœ˜RKšœžœ	žœžœžœžœ˜RKšœžœ	žœžœžœžœ˜RKšœžœ˜%K˜—Kšžœžœ
˜—šžœžœ˜Kšœžœ
˜Kšžœžœ
žœžœ˜Kšžœ
žœ˜Kš
œ˜šžœ	žœ
žœžœ
žœ	ž˜/Kšœ(žœ˜AKš
œ˜Kšžœ
˜—Kš
œ˜š
žœžœ
žœžœ	žœžœž˜6Kš	œ+žœžœ	žœžœ
˜_Kš
œ˜Kšžœ
˜—K˜—K˜
—šžœ˜Kšœ
žœ
žœ˜Kšœžœ
˜Kšžœžœžœžœ˜Sšžœžœ˜Kšœžœ3˜Gšžœ	žœ
žœžœ
žœ	ž˜/Kšžœžœžœ#žœ˜OKš
œ˜Kšžœ
˜—Kšœžœ1˜Eš
žœžœ
žœžœ	žœžœž˜6Kšžœžœžœ&žœ˜RKš
œ˜Kšžœ
˜—K˜—K˜—K˜K˜�—šŸœžœKžœ˜`J™(J™.J™-Jšœžœ˜&Jšœžœ&žœ˜;Jšœ,žœžœ˜FJ˜J˜�—šœžœžœ
žœ
žœ
žœ
žœ
žœ	˜AKšœ
žœ˜)—šŸœžœžœžœžœ
žœ˜NKš
œf˜fKšœžœžœ˜0Kšœžœžœ˜0Kšœžœ
žœI˜[Kš
œ(˜(Kšžœžœ
žœ
žœ˜7Kš
œ˜K˜�—šŸœžœ˜Jšžœ
žœ-˜@Jš
œ-˜-Jš
œ˜J˜�—šŸœ˜)Jš
œ1˜1Jš
œ9˜9Jš
œ5˜5Jš
œ1˜1Jš
œ7˜7Jšœ7žœ˜=Jšœ7žœ˜>Jšœ:žœ˜AJšœ6žœ˜=Jš
œ˜J˜�—š
œC˜CJš
œ-˜-—J˜�Jšžœ
˜—�…—���� Š��.t��