CIRCUIT[Lambda _ 1.0, Temp _ 100] = {Vdd: node;powerSupply: voltage[Vdd, Gnd] = 5.0;! ThymeBasics.thy! CMOS2.0u100C.thyWord, nPrecharge, State, nState, Bit, nBit, BitDecode, nBitDecode, DataI, nDataI, DriveBit, nDriveBit, DriveData, nDriveData, VGnd, DGnd: node;VGndSupply: voltage[VGnd, Gnd] = 0.0;DGndSupply: voltage[DGnd, Gnd] = 0.0;TriStateBuffer: CIRCUIT[Enable, nEnable, DataIn, DataOut | Size _ 32]={PStack, NStack: node;Q1: CTran[nEnable, Vdd, PStack | W _ 2*Size];Q2: CTran[DataIn, PStack, DataOut | W _ 2*Size];Q3: ETran[DataIn, DataOut, NStack | W _ Size]; Q4: ETran[Enable, NStack, DGnd | W _ Size]; };Multiplexor: CIRCUIT[DataIn, DataOut | Size _ 14]={Q2: ETran[Vdd, DataIn, DataOut | W _ Size];};Inverter: CIRCUIT[DataIn, DataOut | Size _ 4]={Q1: CTran[DataIn, Vdd, DataOut | W _ 2*Size];Q2: ETran[DataIn, DataOut, DGnd | W _ Size];};QP1: CTran[State, Vdd, nState | W _ 3, L _ 5]; QP2: CTran[nState, Vdd, State | W _ 3, L _ 5]; Q1: ETran[Word, Bit, State | W _ 4]; Q2: ETran[State, nState, VGnd | W _ 7];Q3: ETran[nState, State, VGnd | W _ 7];Q4: ETran[Word, nBit, nState | W _ 4]; Q5: CTran[nPrecharge, Bit, Vdd | W _ 16];Q6: CTran[nPrecharge, nBit, Vdd | W _ 16]; Q7: ETran[Vdd, DataI, Gnd | W _ 16]; ?: Multiplexor[BitDecode, Bit];?: Multiplexor[nBitDecode, nBit];?: TriStateBuffer[DriveBit, nDriveBit, DataI, nBitDecode];?: TriStateBuffer[DriveBit, nDriveBit, nDataI, BitDecode];?: TriStateBuffer[DriveData, nDriveData, nBitDecode, DataI];?: Inverter[DataI, nDataI];?: voltage[DriveData, Gnd] = 0.0;?: voltage[nDriveData, Gnd] = 5.0;C1: capacitor[Bit, Gnd] = 2.44pF;C2: capacitor[nBit, Gnd] = 2.44pF;C3: capacitor[DataI, Gnd] = 1.0pF;?: RectWave[Word | period _ 100ns, width _ 50ns, tRise _ 10ns, tFall _ 10ns, tDelay _ 50ns];?: RectWave[nPrecharge | OnLevel _ 0V, OffLevel _ 5V, period _ 100ns, width _ 50ns, tRise _ 10ns, tFall _ 10ns];?: RectWave[DriveBit | period _ 100ns, width _ 50ns, tRise _ 10ns, tFall _ 10ns, tDelay _ 50ns];?: RectWave[nDriveBit | OnLevel _ 0V, OffLevel _ 5V, period _ 100ns, width _ 50ns, tRise _ 10ns, tFall _ 10ns, tDelay _ 50ns];};IC[0, Vdd _ 5.0, State _ 4.0, nState _ 0.0];PLOT["CrossRAM bit line", :1ns, -1, 6, Word, nPrecharge, State, nState, Bit, nBit, BitDecode, nBitDecode, DataI, nDataI, DriveBit, nDriveBit, powerSupply^:-1.0mA, VGndSupply^:0.1mA, DGndSupply^:0.5mA];RUN[tMax _ 100ns];    |  CrossRAMWriteStatic.thyLast Edited by: Barth, July 10, 1985 9:20:45 am PDTMultiplexor and Write Buffer, write cycle‌تٍ  ک Jڑœ™Jڑœ3™3Jک ڑدkœک%Jک
Jک%Jک JکJڑœدsœکJک ™)JڑœڈکڈJک%Jڑœ%ک%Jک ڑœ‌œ0کGJکJڑœ!‌œک-Jڑœ$‌œک0Jڑœ$‌œ
ک/Jڑœ!‌œ
ک,Jک—Jک ڑœ‌œک3Jڑœ!‌œ	ک+JکJک —ڑœ
‌œک/Jڑœ!‌œک-Jڑœ"‌œ	ک,JکJک —Jڑœ ‌œ‌œک/Jڑœ ‌œ‌œک/Jڑœ‌œک%Jڑœ ‌œک'Jڑœ ‌œک'Jڑœ‌œک'Jڑœ!‌œک)Jڑœ"‌œک+Jڑœ‌œک%JڑœکJڑœ!ک!Jڑœ:ک:Jڑœ:ک:Jڑœ<ک<JڑœکJک!Jک"Jڑœ!ک!Jڑœ"ک"Jڑœ"ک"Jڑœ\ک\Jڑœ$‌œ‌œ<کpJڑœ`ک`Jڑœ#‌œ‌œKک~Jک —JکJک —Jڑ‌œ*ک,Jڑ‌œإکةJڑ‌œک— …—    	d  ز  