CIRCUIT[Lambda _ 1, Temp _ 100] = { Vdd: node; powerSupply: voltage[Vdd, Gnd] = 5.0; ! ThymeBasics.thy ! CMOS2.0u100C.thy PData, Data, DataI, DriveLow, PDriveLow, nDriveHigh, NnDriveHigh, VVdd, VGnd: node; VVddSupply: inductor[Vdd, VVdd] = (32/7)*5.0nH; VGndSupply: inductor[VGnd, Gnd] = (32/7)*5.0nH; ?: inductor[PData, Data] = 5.0nH; Q1: CTran[DataI, VVdd, nDriveHigh | W _ 32]; Q2: CTran[Vdd, VVdd, nDriveHigh | W _ 32]; Q3: ETran[Vdd, nDriveHigh, NnDriveHigh | W _ 32]; Q4: ETran[DataI, NnDriveHigh, VGnd | W _ 32]; Q5: CTran[DataI, VVdd, PDriveLow | W _ 64]; Q6: CTran[Gnd, PDriveLow, DriveLow | W _ 64]; Q7: ETran[DataI, DriveLow, VGnd | W _ 16]; Q8: ETran[Gnd, DriveLow, VGnd | W _ 16]; Q9: CTran[nDriveHigh, VVdd, PData | W _ 600]; Q10: ETran[DriveLow, PData, VGnd | W _ 300]; C1: capacitor[Data, Gnd] = 50pF; ?: RectWave[DataI | period _ 100ns, width _ 50ns, tRise _ 10ns, tFall _ 10ns, tDelay _ 20ns]; }; PLOT["CrossRAM output buffer", :1ns, -1, 6, Data, DataI, DriveLow, PDriveLow, nDriveHigh, NnDriveHigh, VVddSupply^:10mA, VGndSupply^:10mA]; RUN[tMax _ 100ns]; dCrossRAMOutput.thy Last Edited by: Barth, October 9, 1984 4:26:33 pm PDT Pad Output Buffer Êû˜Jšœ™Jšœ5™5J˜šÏkœ˜#J˜ J˜%J˜J˜JšœÏsœ˜J˜™J™J˜SJ˜/J˜/J˜!J˜Jšœ$œ˜-Jšœ"œ˜*Jšœ)œ˜1Jšœ%œ˜.Jšœ#œ˜+Jšœ%œ˜-Jšœ"œ˜*Jšœ œ˜(Jšœ$œ˜-Jšœ#œ˜,J˜ Jšœ]˜]J™—J˜J˜—Jšœ‡˜‹Jšœ˜—…—:™