CIRCUIT[Lambda _ 1, Temp _ 100] = { Vdd: node; powerSupply: voltage[Vdd, Gnd] = 5.0; ! ThymeBasics.thy ! CMOS2.0u100C.thy Word, nPrecharge, State, nState, Bit, nBit, VGnd, Sense: node; VGndSupply: voltage[VGnd, Gnd] = 0.0; QP1: CTran[State, Vdd, nState | W _ 3, L _ 5]; QP2: CTran[nState, Vdd, State | W _ 3, L _ 5]; Q1: ETran[Word, Bit, State | W _ 4]; Q2: ETran[State, nState, VGnd | W _ 7]; Q3: ETran[nState, State, VGnd | W _ 7]; Q4: ETran[Word, nBit, nState | W _ 4]; Q5: CTran[nPrecharge, Bit, Vdd | W _ 8]; Q6: CTran[nPrecharge, nBit, Vdd | W _ 8]; Q7: CTran[nBit, Vdd, Sense | W _ 8]; Q8: ETran[nBit, Sense, Gnd | W _ 4]; C1: capacitor[Bit, Gnd] = 2.44pF; C2: capacitor[nBit, Gnd] = 2.44pF; C3: capacitor[Sense, Gnd] = 0.1pF; ?: RectWave[Word | period _ 100ns, width _ 50ns, tRise _ 10ns, tFall _ 10ns, tDelay _ 50ns]; ?: RectWave[nPrecharge | OnLevel _ 0V, OffLevel _ 5V, period _ 100ns, width _ 50ns, tRise _ 10ns, tFall _ 10ns]; }; IC[0, Vdd _ 5.0, State _ 3.3, nState _ 0.0]; PLOT["CrossRAM bit line", :1ns, -1, 6, Word, nPrecharge, State, nState, Bit, nBit, Sense, powerSupply^:-1.0mA, VGndSupply^:0.1mA]; RUN[tMax _ 100ns]; `CrossRAMBitLineStatic.thy Last Edited by: Barth, October 8, 1984 3:38:55 pm PDT Bit Line Ê&˜Jšœ™Jšœ5™5J˜šÏkœ˜#J˜ J˜%J˜J˜JšœÏsœ˜J˜™J˜>J˜%J˜Jšœ œœ˜/Jšœ œœ˜/Jšœœ˜%Jšœ œ˜'Jšœ œ˜'Jšœœ˜'Jšœ!œ˜(Jšœ"œ˜*Jšœœ˜%Jšœœ˜$Jšœ!˜!Jšœ"˜"Jšœ"˜"Jšœ\˜\Jšœ$œœ<˜pJ˜J™—J˜J˜—Jšœ*˜,Jšœ~˜‚Jšœ˜—…—€