CIRCUIT[Lambda _ 1, Temp _ 100] = { Vdd: node; powerSupply: voltage[Vdd, Gnd] = 5.0; ! ThymeBasics.thy ! CMOS2.0u100C.thy AddressIn, nAddressIn, NAnd1, NAnd2, NAnd, And, VGnd: node; VGndSupply: voltage[VGnd, Gnd] = 0.0; Q1: CTran[AddressIn, Vdd, nAddressIn | W _ 16]; Q2: ETran[AddressIn, nAddressIn, VGnd | W _ 8]; Q3: CTran[nAddressIn, Vdd, NAnd | W _ 16]; Q4: CTran[Vdd, Vdd, NAnd | W _ 16]; Q5: CTran[Vdd, Vdd, NAnd | W _ 16]; Q6: ETran[nAddressIn, NAnd, NAnd1 | W _ 16]; Q7: ETran[Vdd, NAnd1, NAnd2 | W _ 16]; Q8: ETran[Vdd, NAnd2, VGnd | W _ 16 ]; Q9: CTran[NAnd, Vdd, And | W _ 32]; Q10: ETran[NAnd, And, VGnd | W _ 16]; C1: capacitor[And, Gnd] = 3.09pF; C2: capacitor[nAddressIn, Gnd] = 0.387pF; ?: RectWave[AddressIn | period _ 100ns, width _ 50ns, tRise _ 10ns, tFall _ 10ns, tDelay _ 20ns]; }; PLOT["CrossRAM Address Driver", :1ns, -1, 6, AddressIn, nAddressIn, NAnd1, NAnd2, NAnd, And, powerSupply^:-0.5mA, VGndSupply^:0.5mA]; RUN[tMax _ 100ns]; ^CrossRAMAnd3.thy Last Edited by: Barth, October 5, 1984 2:47:33 pm PDT Address Driver ʘJšœ™Jšœ5™5J˜šÏkœ˜#J˜ J˜%J˜J˜JšœÏsœ ˜J˜™J™Jšœ;˜;J˜%J˜Jšœ'œ˜0Jšœ(œ˜/Jšœ"œ˜+Jšœœ˜$Jšœœ˜$Jšœ$œ˜,Jšœœ˜&Jšœœ˜&Jšœœ˜#Jšœœ˜%Jšœ!˜!Jšœ)˜)Jšœa˜aJ™—J˜J˜—Jšœ˜…Jšœ˜—…—È*