DIRECTORY ChipCreate; CoreSSI: CEDAR DEFINITIONS = BEGIN OPEN ChipCreate; CreateInverter: PROC [design: Design, width: NAT _ 4, ratio: REAL _ 2.5] RETURNS [ct: CellType]; CreateTristateBuffer: PROC [design: Design, width: NAT _ 4, ratio: REAL _ 2.5] RETURNS [ct: CellType]; CreateNAnd: PROC [design: Design, inputCount: NAT _ 2, width: NAT _ 4, ratio: REAL _ 2.5] RETURNS [ct: CellType]; CreateAnd: PROC [design: Design, inputCount: NAT _ 2, width: NAT _ 4, ratio: REAL _ 2.5] RETURNS [ct: CellType]; CreateNOr: PROC [design: Design, inputCount: NAT _ 2, width: NAT _ 4, ratio: REAL _ 2.5] RETURNS [ct: CellType]; CreateOr: PROC [design: Design, inputCount: NAT _ 2, width: NAT _ 4, ratio: REAL _ 2.5] RETURNS [ct: CellType]; END. ςCoreSSI.mesa Copyright c 1985 by Xerox Corporation. All rights reversed. Last Edited by: Barth, July 10, 1985 8:06:03 pm PDT Width refers to the effective N channel width. As transistors are stacked the actual width is increased accordingly. Ratio refers to the amount by which the effective N channel width is multiplied to compute the effective P channel width. The effective P channel width is rounded up to the nearest integer lambda. Ports: Vdd[top, 0], Gnd[bottom, 0], Input[left, 0], Output[right, 0] Ports: Vdd, Gnd, nInput, Drive, nDrive, Output Ports: Vdd, Gnd, Input[0..inputCount), nOutput Ports: Vdd, Gnd, Input[0..inputCount), Output Ports: Vdd, Gnd, Input[0..inputCount), nOutput Ports: Vdd, Gnd, Input[0..inputCount), Output Κn˜J– "Cedar" stylešœ ™ Jšœ Οmœ1™