<> <> Imports RoseTypes; Library Transistors; CELLTYPE "Inverter" PORTS [Vdd, Gnd, Input < BOOL, Output > BOOL] EvalSimple Output _ NOT Input; Expand p: pE[gate: Input, ch1: Vdd, ch2: Output]; n: nE[gate: Input, ch1: Output, ch2: Gnd] ENDCELLTYPE; CELLTYPE "Nand2" PORTS [Vdd, Gnd, Input1, Input2 < BOOL, Output > BOOL] EvalSimple Output _ NOT (Input1 AND Input2); Expand stack: BIT; p1: pE[gate: Input1, ch1: Vdd, ch2: Output]; p2: pE[gate: Input2, ch1: Vdd, ch2: Output]; n1: nE[gate: Input1, ch1: Output, ch2: stack]; n2: nE[gate: Input2, ch1: stack, ch2: Gnd] ENDCELLTYPE; CELLTYPE "Nor2" PORTS [Vdd, Gnd, Input1, Input2 < BOOL, Output > BOOL] EvalSimple Output _ NOT (Input1 OR Input2); Expand stack: BIT; p1: pE[gate: Input1, ch1: Vdd, ch2: stack]; p2: pE[gate: Input2, ch1: stack, ch2: Output]; n1: nE[gate: Input1, ch1: Output, ch2: Gnd]; n2: nE[gate: Input2, ch1: Output, ch2: Gnd] ENDCELLTYPE; CELLTYPE "Nand3" PORTS [Vdd, Gnd, Input1, Input2, Input3 < BOOL, Output > BOOL] EvalSimple Output _ NOT (Input1 AND Input2 AND Input3); Expand stack1, stack2: BIT; p1: pE[gate: Input1, ch1: Vdd, ch2: Output]; p2: pE[gate: Input2, ch1: Vdd, ch2: Output]; p3: pE[gate: Input3, ch1: Vdd, ch2: Output]; n1: nE[gate: Input1, ch1: Output, ch2: stack1]; n2: nE[gate: Input2, ch1: stack1, ch2: stack2]; n3: nE[gate: Input3, ch1: stack2, ch2: Gnd] ENDCELLTYPE; CELLTYPE "And3" PORTS [Vdd, Gnd, Input1, Input2, Input3 < BOOL, Output > BOOL] EvalSimple Output _ Input1 AND Input2 AND Input3; Expand nandOut: BIT; nand: Nand3[Output: nandOut]; invert: Inverter[Input: nandOut] ENDCELLTYPE; CELLTYPE "TristateBuffer" PORTS [Vdd, Gnd, nDataIn, Drive, nDrive < BOOL, Output = BOOL -- tristate ] EvalSimple IF (Drive AND nDrive) OR (NOT Drive AND NOT nDrive) THEN RoseTypes.Stop["Bad control signals in tristate buffer", $FailedAssertion]; Output _ NOT nDataIn; drive[Output] _ IF Drive THEN drive ELSE ignore; Expand nstack, pstack: BIT; p1: pE[gate: nDrive, ch1: Vdd, ch2: pstack]; p2: pE[gate: nDataIn, ch1: pstack, ch2: Output]; n1: nE[gate: nDataIn, ch1: Output, ch2: nstack]; n2: nE[gate: Drive, ch1: nstack, ch2: Gnd] ENDCELLTYPE