<> <> <> DIRECTORY Core; SSI: CEDAR DEFINITIONS = BEGIN OPEN Core; <> <<>> <> CreateInverter: PROC [design: Design, width: NAT _ 4, ratio: REAL _ 2.5] RETURNS [ct: CellType]; <> CreateTristateBuffer: PROC [design: Design, width: NAT _ 4, ratio: REAL _ 2.5] RETURNS [ct: CellType]; <> CreateNAnd: PROC [design: Design, inputCount: NAT _ 2, width: NAT _ 4, ratio: REAL _ 2.5] RETURNS [ct: CellType]; <> CreateAnd: PROC [design: Design, inputCount: NAT _ 2, width: NAT _ 4, ratio: REAL _ 2.5] RETURNS [ct: CellType]; <> CreateNOr: PROC [design: Design, inputCount: NAT _ 2, width: NAT _ 4, ratio: REAL _ 2.5] RETURNS [ct: CellType]; <> CreateOr: PROC [design: Design, inputCount: NAT _ 2, width: NAT _ 4, ratio: REAL _ 2.5] RETURNS [ct: CellType]; END.