SSI:
CEDAR
DEFINITIONS =
BEGIN OPEN Core;
Width refers to the effective N channel width. As transistors are stacked the actual width is increased accordingly. Ratio refers to the amount by which the effective N channel width is multiplied to compute the effective P channel width. The effective P channel width is rounded up to the nearest integer lambda.
Ports: Vdd, Gnd, Input, Output
CreateInverter: PROC [design: Design, width: NAT ← 4, ratio: REAL ← 2.5] RETURNS [ct: CellType];
Ports: Vdd, Gnd, nInput, Drive, nDrive, Output
CreateTristateBuffer: PROC [design: Design, width: NAT ← 4, ratio: REAL ← 2.5] RETURNS [ct: CellType];
Ports: Vdd, Gnd, Input[0..inputCount), nOutput
CreateNAnd: PROC [design: Design, inputCount: NAT ← 2, width: NAT ← 4, ratio: REAL ← 2.5] RETURNS [ct: CellType];
Ports: Vdd, Gnd, Input[0..inputCount), Output
CreateAnd: PROC [design: Design, inputCount: NAT ← 2, width: NAT ← 4, ratio: REAL ← 2.5] RETURNS [ct: CellType];
Ports: Vdd, Gnd, Input[0..inputCount), nOutput
CreateNOr: PROC [design: Design, inputCount: NAT ← 2, width: NAT ← 4, ratio: REAL ← 2.5] RETURNS [ct: CellType];
Ports: Vdd, Gnd, Input[0..inputCount), Output
CreateOr: PROC [design: Design, inputCount: NAT ← 2, width: NAT ← 4, ratio: REAL ← 2.5] RETURNS [ct: CellType];