
    <<RAMArrayTest.mesa>>
    <<Last edited by Barth, March 14, 1985 8:18:07 pm PST>>


    DIRECTORY
        BitOps, RAMArray, RoseTypes, RoseCreate, RoseRun, SwitchTypes;

    RAMArrayTest: CEDAR PROGRAM
        IMPORTS BitOps, RoseCreate, RoseRun, RoseTypes
        SHARES RAMArray =

    BEGIN OPEN
        BitOps, RAMArray;

    PrimitiveRAMTest: RoseTypes.CellTestProc =
        BEGIN
        instructions: RAMArrayIORef _ NARROW[io];
        state: RAMArrayStateRef _ NARROW[stateAsAny];
        args: REF RAMArrayArgs _ NARROW[testeeType.typeData];
        drive: Drive _ NARROW[driveAsAny];
            BEGIN OPEN args, state, instructions;
            high: SwitchTypes.SwitchVal _ [[driveStrong, driveStrong, none], H, 0];
            low: SwitchTypes.SwitchVal _ [[driveStrong, none, driveStrong], L, 0];
            tristate: SwitchTypes.SwitchVal _ [[none, none, none], X, 0];
            select0: NAT = 0;
            bit0: NAT = rows;

                Access: PROC [write: BOOL, row: NAT, data: LONG CARDINAL] = {

                    SetColumnLines: PROC [value: SwitchTypes.SwitchVal] = {
                        valueIndex: CARDINAL _ rows;
                        FOR col:CARDINAL IN [0..columns) DO
                            values[valueIndex] _ value;
                            values[valueIndex+1] _ value;
                            valueIndex _ valueIndex+2;
                            ENDLOOP;
                    };

                    d: BitDWord _ ILID[data, BitDWordZero, 32, 0, 32];
                    <<precharge>>
                    SetColumnLines[high];
                [] _ RoseRun.Eval[handle];
                    SetColumnLines[tristate];
                [] _ RoseRun.Eval[handle];
                    <<>>
                    <<enable select line>>
                    values[row] _ high;
                    <<if write then enable write drivers>>
                    IF write THEN {
                        valueIndex: CARDINAL _ rows;
                        FOR col:CARDINAL IN [0..columns) DO
                            IF EBFD[d, columns, col] THEN {
                                values[valueIndex] _ high;
                                values[valueIndex+1]  _ low;
                            } ELSE {
                                values[valueIndex] _ low;
                                values[valueIndex+1]  _ high;
                                };
                            valueIndex _ valueIndex+2;
                            ENDLOOP;
                        };
                [] _ RoseRun.Eval[handle];
                    <<if read then check data>>
                    IF NOT write THEN {
                        valueIndex: CARDINAL _ rows;
                        FOR col:CARDINAL IN [0..columns) DO
                            bitOfData: BOOL _ EBFD[d, columns, col];
                            IF (bitOfData AND (values[valueIndex].val # H OR values[valueIndex+1].val # L)) OR (NOT bitOfData AND (values[valueIndex].val # L 
                            OR values[valueIndex+1].val # H)) THEN RoseTypes.Stop["Read failed", $FailedAssertion];
                            valueIndex _ valueIndex+2;
                            ENDLOOP;
                        };
                    <<disable select line>>
                    values[row] _ low;
                    <<if write then disable write drivers>>
                    IF write THEN SetColumnLines[tristate];
                [] _ RoseRun.Eval[handle];
                    };

            Vdd _ high;
            Gnd _ low;
            IF rows<2 OR columns>32 THEN RoseTypes.Stop["Too many columns in RAM for this test procedure", $FailedAssertion];
            FOR row:CARDINAL IN [0..rows) DO
            values[row] _ [[input, none, input], L, 0];
            ENDLOOP;
            [] _ RoseRun.Eval[handle];
            FOR row:CARDINAL IN [0..rows) DO
            IF values[row] # [[input, none, input], L, 0] THEN RoseTypes.Stop["select lines are crazy", $FailedAssertion];
            ENDLOOP;
            Access[write: TRUE, row: 0, data: 0];
            Access[write: TRUE, row: 1, data: LAST[LONG CARDINAL]];
            Access[write: FALSE, row: 0, data: 0];
            Access[write: FALSE, row: 1, data: LAST[LONG CARDINAL]];
                values[select0] _ high;
                values[select0+1] _ high;
            [] _ RoseRun.Eval[handle];
                {
                    valueIndex: CARDINAL _ bit0;
                    FOR col:CARDINAL IN [0..columns) DO
                        IF values[valueIndex].val # X OR values[valueIndex+1].val # X THEN RoseTypes.Stop["data line is incorrect for multiple rows", 
                        $FailedAssertion];
                        valueIndex _ valueIndex+2;
                        ENDLOOP;
                    FOR row:CARDINAL IN [0..2) DO
                        FOR col:CARDINAL IN [0..columns) DO
                            memIndex: NAT _ row*columns+col;
                            IF memory[memIndex].state # X OR memory[memIndex].nstate # X THEN RoseTypes.Stop["state bit is incorrect for multiple rows", 
                            $FailedAssertion];
                            ENDLOOP;
                        ENDLOOP;
                    };
            END;
        END;

    ctest: RoseTypes.CellTest _ NEW[RoseTypes.CellTestRep _ ["Primitive", PrimitiveRAMTest, TRUE]];
    ct: RoseTypes.CellType _ RoseCreate.GetCellType["RAMArray23dWd"];
    [] _ RoseCreate.SetTest[ctest, ct, TRUE];

    END.