RAMArrayTest.mesa
Last edited by Barth, March 14, 1985 8:18:07 pm PST
DIRECTORY
BitOps, RAMArray, RoseTypes, RoseCreate, RoseRun, SwitchTypes;
RAMArrayTest: CEDAR PROGRAM
IMPORTS BitOps, RoseCreate, RoseRun, RoseTypes
SHARES RAMArray =
BEGIN OPEN
BitOps, RAMArray;
PrimitiveRAMTest: RoseTypes.CellTestProc =
BEGIN
instructions: RAMArrayIORef ← NARROW[io];
state: RAMArrayStateRef ← NARROW[stateAsAny];
args: REF RAMArrayArgs ← NARROW[testeeType.typeData];
drive: Drive ← NARROW[driveAsAny];
BEGIN OPEN args, state, instructions;
high: SwitchTypes.SwitchVal ← [[driveStrong, driveStrong, none], H, 0];
low: SwitchTypes.SwitchVal ← [[driveStrong, none, driveStrong], L, 0];
tristate: SwitchTypes.SwitchVal ← [[none, none, none], X, 0];
select0: NAT = 0;
bit0: NAT = rows;
Access: PROC [write: BOOL, row: NAT, data: LONG CARDINAL] = {
SetColumnLines: PROC [value: SwitchTypes.SwitchVal] = {
valueIndex: CARDINAL ← rows;
FOR col:CARDINAL IN [0..columns) DO
values[valueIndex] ← value;
values[valueIndex+1] ← value;
valueIndex ← valueIndex+2;
ENDLOOP;
};
d: BitDWord ← ILID[data, BitDWordZero, 32, 0, 32];
precharge
SetColumnLines[high];
[] ← RoseRun.Eval[handle];
SetColumnLines[tristate];
[] ← RoseRun.Eval[handle];
enable select line
values[row] ← high;
if write then enable write drivers
IF write THEN {
valueIndex: CARDINAL ← rows;
FOR col:CARDINAL IN [0..columns) DO
IF EBFD[d, columns, col] THEN {
values[valueIndex] ← high;
values[valueIndex+1] ← low;
} ELSE {
values[valueIndex] ← low;
values[valueIndex+1] ← high;
};
valueIndex ← valueIndex+2;
ENDLOOP;
};
[] ← RoseRun.Eval[handle];
if read then check data
IF NOT write THEN {
valueIndex: CARDINAL ← rows;
FOR col:CARDINAL IN [0..columns) DO
bitOfData: BOOLEBFD[d, columns, col];
IF (bitOfData AND (values[valueIndex].val # H OR values[valueIndex+1].val # L)) OR (NOT bitOfData AND (values[valueIndex].val # L OR values[valueIndex+1].val # H)) THEN RoseTypes.Stop["Read failed", $FailedAssertion];
valueIndex ← valueIndex+2;
ENDLOOP;
};
disable select line
values[row] ← low;
if write then disable write drivers
IF write THEN SetColumnLines[tristate];
[] ← RoseRun.Eval[handle];
};
Vdd ← high;
Gnd ← low;
IF rows<2 OR columns>32 THEN RoseTypes.Stop["Too many columns in RAM for this test procedure", $FailedAssertion];
FOR row:CARDINAL IN [0..rows) DO
values[row] ← [[input, none, input], L, 0];
ENDLOOP;
[] ← RoseRun.Eval[handle];
FOR row:CARDINAL IN [0..rows) DO
IF values[row] # [[input, none, input], L, 0] THEN RoseTypes.Stop["select lines are crazy", $FailedAssertion];
ENDLOOP;
Access[write: TRUE, row: 0, data: 0];
Access[write: TRUE, row: 1, data: LAST[LONG CARDINAL]];
Access[write: FALSE, row: 0, data: 0];
Access[write: FALSE, row: 1, data: LAST[LONG CARDINAL]];
values[select0] ← high;
values[select0+1] ← high;
[] ← RoseRun.Eval[handle];
{
valueIndex: CARDINAL ← bit0;
FOR col:CARDINAL IN [0..columns) DO
IF values[valueIndex].val # X OR values[valueIndex+1].val # X THEN RoseTypes.Stop["data line is incorrect for multiple rows", $FailedAssertion];
valueIndex ← valueIndex+2;
ENDLOOP;
FOR row:CARDINAL IN [0..2) DO
FOR col:CARDINAL IN [0..columns) DO
memIndex: NAT ← row*columns+col;
IF memory[memIndex].state # X OR memory[memIndex].nstate # X THEN RoseTypes.Stop["state bit is incorrect for multiple rows", $FailedAssertion];
ENDLOOP;
ENDLOOP;
};
END;
END;
ctest: RoseTypes.CellTest ← NEW[RoseTypes.CellTestRep ← ["Primitive", PrimitiveRAMTest, TRUE]];
ct: RoseTypes.CellType ← RoseCreate.GetCellType["RAMArray23dWd"];
[] ← RoseCreate.SetTest[ctest, ct, TRUE];
END.