<> <> <> <<>> DIRECTORY Core, Pads, SSI, Transistor; PadsImpl: CEDAR PROGRAM IMPORTS Core, SSI, Transistor EXPORTS Pads = BEGIN OPEN Core; CreateBasicInputPad: PUBLIC PROC [design: Design] RETURNS [ct: CellType] = { name: ROPE _ "BasicInputPad"; IF (ct _ LookupCellType[design, name])=NIL THEN { invert: CellType _ SSI.CreateInverter[design: design, width: 64, ratio: 0.125]; ct _ CreateCellType[design: design, cellTypeName: name]; CreatePort[on: ct, name: "Vdd"]; CreatePort[on: ct, name: "Gnd"]; CreatePort[on: ct, name: "Pad"]; CreatePort[on: ct, name: "nOutput", direction: output]; CreateCell[in: ct, type: invert, bind: "Input: Pad, Output: nOutput"]; }; }; CreateInputPad: PUBLIC PROC [design: Design] RETURNS [ct: CellType] = { name: ROPE _ "InputPad"; IF (ct _ LookupCellType[design, name])=NIL THEN { bp: CellType _ CreateBasicInputPad[design: design]; invert: CellType _ SSI.CreateInverter[design: design, width: 8]; ct _ CreateCellType[design: design, cellTypeName: name]; CreatePort[on: ct, name: "Vdd"]; CreatePort[on: ct, name: "Gnd"]; CreatePort[on: ct, name: "Pad"]; CreatePort[on: ct, name: "Output", direction: output]; CreateNet[in: ct, name: "nOutput"]; CreateCell[in: ct, type: bp]; CreateCell[in: ct, type: invert, bind: "Input: nOutput, Output: Output"]; }; }; CreateDifferentialInputPad: PUBLIC PROC [design: Design] RETURNS [ct: CellType] = { name: ROPE _ "DifferentialInputPad"; IF (ct _ LookupCellType[design, name])=NIL THEN { bp: CellType _ CreateBasicInputPad[design: design]; invert8: CellType _ SSI.CreateInverter[design: design, width: 8]; invert4: CellType _ SSI.CreateInverter[design: design, width: 4]; ct _ CreateCellType[design: design, cellTypeName: name]; CreatePort[on: ct, name: "Vdd"]; CreatePort[on: ct, name: "Gnd"]; CreatePort[on: ct, name: "Pad"]; CreatePort[on: ct, name: "Output", direction: output]; CreatePort[on: ct, name: "nOutput", direction: output]; CreateNet[in: ct, name: "nbpOut"]; CreateNet[in: ct, name: "bpOut"]; CreateCell[in: ct, type: bp, bind: "nOutput: nbpOut"]; CreateCell[in: ct, type: invert8, bind: "Input: nbpOut, Output: Output"]; CreateCell[in: ct, type: invert4, bind: "Input: nbpOut, Output: bpOut"]; CreateCell[in: ct, type: invert8, bind: "Input: bpOut, Output: nOutput"]; }; }; CreateBidirectionalPad: PUBLIC PROC [design: Design] RETURNS [ct: CellType] = { name: ROPE _ "BidirectionalPad"; IF (ct _ LookupCellType[design, name])=NIL THEN { bp: CellType _ CreateBasicInputPad[design: design]; tristate: CellType _ SSI.CreateTristateBuffer[design: design, width: 32]; nand2: CellType _ SSI.CreateNAnd[design: design, width: 8]; nor2: CellType _ SSI.CreateNOr[design: design, width: 8]; p: CellType _ Transistor.CreateTransistor[design: design, type: pE, width: 600]; n: CellType _ Transistor.CreateTransistor[design: design, width: 300]; ct _ CreateCellType[design: design, cellTypeName: name]; CreatePort[on: ct, name: "Vdd"]; CreatePort[on: ct, name: "Gnd"]; CreatePort[on: ct, name: "Read"]; CreatePort[on: ct, name: "nRead"]; CreatePort[on: ct, name: "Write"]; CreatePort[on: ct, name: "nWrite"]; CreatePort[on: ct, name: "Pad", direction: bidirectional]; CreatePort[on: ct, name: "Data", direction: bidirectional]; CreateNet[in: ct, name: "nandOut"]; CreateNet[in: ct, name: "norOut"]; CreateNet[in: ct, name: "nbpOut"]; CreateCell[in: ct, type: bp, bind: "nOutput: nbpOut"]; CreateCell[in: ct, type: tristate, bind: "nInput: nbpOut, Drive: Write, nDrive: nWrite, Output: Data"]; CreateCell[in: ct, type: nand2, bind: "Input0: Read, Input1: Data, nOutput: nandOut"]; CreateCell[in: ct, type: nor2, bind: "Input0: nRead, Input1: Data, nOutput: norOut"]; CreateCell[in: ct, type: p, bind: "gate: nandOut, ch1: Vdd, ch2: Pad"]; CreateCell[in: ct, type: n, bind: "gate: norOut, ch1: Pad, ch2: Gnd"]; }; }; END.