Decoder.rose
Last Edited by: Barth, July 1, 1985 5:51:35 pm PDT
Imports BitOps, IO, NumTypes, Rope, RoseExtras;
Library SSI, Transistors;
CELLTYPE "
WordDriver"
PORTS [Vdd, Gnd, Access, nDecode<BOOL, Word>BOOL]
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decode, nwordStack, nword: BIT;
invertDecode: Inverter[Input: nDecode, Output: decode];
p: pE[gate: Access, ch1: Vdd, ch2: nword];
n: nE[gate: decode, ch1: nword, ch2: nwordStack];
n: nE[gate: Access, ch1: nwordStack, ch2: Gnd];
invertWord: Inverter[Input: nword, Output: Word]
ENDCELLTYPE;
CELLTYPE "
WordDriverPair"
PORTS [Vdd, Gnd, HighSelect, LowSelect, Access, nDecode<BOOL, WordHigh, WordLow>BOOL]
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ntreeDecodeHigh, ntreeDecodeLow: BIT;
p: pE[gate: HighSelect, ch1: Vdd, ch2: ntreeDecodeHigh];
n: nE[gate: HighSelect, ch1: nDecode, ch2: ntreeDecodeHigh];
p: pE[gate: LowSelect, ch1: Vdd, ch2: ntreeDecodeLow];
n: nE[gate: LowSelect, ch1: nDecode, ch2: ntreeDecodeLow];
highWord: WordDriver[nDecode: ntreeDecodeHigh, Word: WordHigh];
lowWord: WordDriver[nDecode: ntreeDecodeLow, Word: WordLow]
ENDCELLTYPE;
CELLTYPE "
DecoderDriver"
PORTS [Vdd, Gnd, Address<BOOL, AdrBit, nAdrBit>BOOL]
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naddress: BIT;
invertAddress: Inverter[Input: Address, Output: naddress];
invertnAddress: Inverter[Input: naddress, Output: AdrBit];
invertnAdrBit: Inverter[Input: Address, Output: nAdrBit]
ENDCELLTYPE;
CELLTYPE "
DecoderDriverSequence"
PORTS [Vdd, Gnd, Address<INT[8], AdrBit, nAdrBit>INT[8]]
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Cedar
RoseExtras.Flatten[thisCell, to, "Address", 8];
RoseExtras.Flatten[thisCell, to, "AdrBit", 8];
RoseExtras.Flatten[thisCell, to, "nAdrBit", 8];
FOR column:
CARDINAL
IN [0..8)
DO
[] ← to.class.CellInstance[erInstance: to.instance, instanceName: IO.PutFR["DecoderDriver%g", IO.int[column]], typeName: "DecoderDriver", interfaceNodes: IO.PutFR["Address: Address%g, AdrBit: AdrBit%g, nAdrBit: nAdrBit%g", IO.int[column], IO.int[column], IO.int[column]]];
ENDLOOP;
};
ENDCELLTYPE;
PairDecoder:
LAMBDA [addressDiv2: |
CARDINAL|]
RETURN
CELLTYPE
NameMaker
name ← IO.PutFR["PairDecoder%g", IO.int[addressDiv2]]
PORTS [Vdd, Gnd, Access<BOOL, AdrBit, nAdrBit<INT[8], WordHigh, WordLow>BOOL]
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Cedar
RoseExtras.Flatten[thisCell, to, "AdrBit", 8];
RoseExtras.Flatten[thisCell, to, "nAdrBit", 8];
[] ← to.class.NodeInstance[erInstance: to.instance, name: "stack0", type: SwitchTypes.bitType];
FOR column:
CARDINAL
IN [0..7)
DO
adrBitName: ROPE ← IF EBFW[addressDiv2, column, 8] THEN IO.rope["AdrBit"] ELSE IO.rope["nAdrBit"];
stackName: ROPE;
IF column<6
THEN {
stackName ← IO.PutFR["stack%g", IO.int[column+1]];
[] ← to.class.NodeInstance[erInstance: to.instance, name: stackName, type: SwitchTypes.bitType];
}
ELSE stackName ← "Gnd";
[] ← to.class.CellInstance[erInstance: to.instance, instanceName: IO.PutFR["pu%g", IO.int[column]], typeName: "pE", interfaceNodes: IO.PutFR["gate: %g%g, ch1: Vdd, ch2: nDecode", adrBitName, IO.int[column]]];
[] ← to.class.CellInstance[erInstance: to.instance, instanceName: IO.PutFR["pd%g", IO.int[column]], typeName: "nE", interfaceNodes: IO.PutFR["gate: %g%g, ch1: stack%g, ch2: %g", adrBitName, IO.int[column], IO.int[column], IO.rope[stackName]]];
ENDLOOP;
;
wdp: WordDriverPair[HighSelect: AdrBit7, LowSelect: nAdrBit7, nDecode: stack0]
ENDCELLTYPE;
Cedar
CrossRAMPairDecoders:
PROC = {
FOR rowPair:
INT
IN [0..60)
DO
[] ← PairDecoder[rowPair];
ENDLOOP;
};
CrossRAMPairDecoders[];
;
CELLTYPE "
CrossDecoder"
PORTS [Vdd, Gnd, Access<BOOL, Address<INT[8], Word>INT[256]]
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AdrBit, nAdrBit: INT[8];
decoderBuffer: DecoderDriverSequence[Address: Address, AdrBit: AdrBit, nAdrBit: nAdrBit];
Cedar
RoseExtras.Flatten[thisCell, to, "Word", 256];
FOR rowPair:
CARDINAL
IN [0..60)
DO
[] ← to.class.CellInstance[erInstance: to.instance, instanceName: IO.PutFR["decoder%g", IO.int[rowPair]], typeName: IO.PutFR["PairDecoder%g", IO.int[rowPair]], interfaceNodes: IO.PutFR["WordHigh: Word%g, WordLow: Word%g", IO.int[(2*rowPair)+1], IO.int[2*rowPair]]];
ENDLOOP;
ENDCELLTYPE