CrossRAMWrite.thy
Last Edited by: Barth, October 4, 1984 5:27:14 pm PDT
CIRCUIT[Lambda ← 1, Temp ← 100] = {
Vdd: node;
powerSupply: voltage[Vdd, Gnd] = 5.0;
! ThymeBasics.thy
! CMOS2.0u100C.thy
Multiplexor and Write Buffer, write cycle
Word, nPrecharge, State, nState, Bit, nBit, BitDecode, nBitDecode, DataI, nDataI, DriveBit, nDriveBit, DriveData, nDriveData, VGnd, DGnd: node;
VGndSupply: voltage[VGnd, Gnd] = 0.0;
DGndSupply: voltage[DGnd, Gnd] = 0.0;
TriStateBuffer: CIRCUIT[Enable, nEnable, DataIn, DataOut | Size ← 32]={
PStack, NStack: node;
Q1: CTran[nEnable, Vdd, PStack | W ← 2*Size];
Q2: CTran[DataIn, PStack, DataOut | W ← 2*Size];
Q3: ETran[DataIn, DataOut, NStack | W ← Size];
Q4: ETran[Enable, NStack, DGnd | W ← Size];
};
Multiplexor: CIRCUIT[DataIn, DataOut | Size ← 14]={
Q2: ETran[Vdd, DataIn, DataOut | W ← Size];
};
Inverter: CIRCUIT[DataIn, DataOut | Size ← 4]={
Q1: CTran[DataIn, Vdd, DataOut | W ← 2*Size];
Q2: ETran[DataIn, DataOut, DGnd | W ← Size];
};
Q1: ETran[Word, Bit, State | W ← 4];
Q2: ETran[State, nState, VGnd | W ← 7];
Q3: ETran[nState, State, VGnd | W ← 7];
Q4: ETran[Word, nBit, nState | W ← 4];
Q5: CTran[nPrecharge, Bit, Vdd | W ← 16];
Q6: CTran[nPrecharge, nBit, Vdd | W ← 16];
Q7: ETran[Vdd, DataI, Gnd | W ← 16];
?: Multiplexor[BitDecode, Bit];
?: Multiplexor[nBitDecode, nBit];
?: TriStateBuffer[DriveBit, nDriveBit, DataI, nBitDecode];
?: TriStateBuffer[DriveBit, nDriveBit, nDataI, BitDecode];
?: TriStateBuffer[DriveData, nDriveData, nBitDecode, DataI];
?: Inverter[DataI, nDataI];
?: voltage[DriveData, Gnd] = 0.0;
?: voltage[nDriveData, Gnd] = 5.0;
C1: capacitor[Bit, Gnd] = 2.44pF;
C2: capacitor[nBit, Gnd] = 2.44pF;
C3: capacitor[DataI, Gnd] = 1.0pF;
?: RectWave[Word | period ← 100ns, width ← 50ns, tRise ← 10ns, tFall ← 10ns, tDelay ← 50ns];
?: RectWave[nPrecharge | OnLevel ← 0V, OffLevel ← 5V, period ← 100ns, width ← 50ns, tRise ← 10ns, tFall ← 10ns];
?: RectWave[DriveBit | period ← 100ns, width ← 50ns, tRise ← 10ns, tFall ← 10ns, tDelay ← 50ns];
?: RectWave[nDriveBit | OnLevel ← 0V, OffLevel ← 5V, period ← 100ns, width ← 50ns, tRise ← 10ns, tFall ← 10ns, tDelay ← 50ns];
};
IC[0, Vdd ← 5.0, State ← 4.0, nState ← 0.0];
PLOT["CrossRAM bit line", :1ns, -1, 6, Word, nPrecharge, State, nState, Bit, nBit, BitDecode, nBitDecode, DataI, nDataI, DriveBit, nDriveBit, powerSupply^:-1.0mA, VGndSupply^:0.1mA, DGndSupply^:0.5mA];
RUN[tMax ← 100ns];