<> <> CIRCUIT[Lambda _ 1, Temp _ 100] = { Vdd: node; powerSupply: voltage[Vdd, Gnd] = 5.0; ! ThymeBasics.thy ! CMOS2.0u100C.thy <> <<>> PhBb, NotWord, NotWord1, Word, VGnd: node; VGndSupply: voltage[VGnd, Gnd] = 0.0; Q1: CTran[PhBb, Vdd, NotWord | W _ 10]; Q2: ETran[Vdd, NotWord, NotWord1 | W _ 10]; Q3: ETran[PhBb, NotWord1, VGnd | W _ 10]; Q4: CTran[NotWord, Vdd, Word | W _ 60]; Q5: ETran[NotWord, Word, VGnd | W _ 30]; C1: capacitor[Word, Gnd] = 6.71pF; ?: RectWave[PhBb | period _ 100ns, width _ 50ns, tRise _ 10ns, tFall _ 10ns]; <<>> }; IC[0, Vdd _ 5.0, NotWord _ 5.0, NotWord1 _ 5.0]; PLOT["CrossRAM word line", :1ns, -1, 6, PhBb, NotWord, NotWord1, Word, powerSupply^:-1.0mA, VGndSupply^:1.0mA]; RUN[tMax _ 100ns];