CrossRAMWordLine.thy
Last Edited by: Barth, October 8, 1984 2:19:35 pm PDT
CIRCUIT[Lambda ← 1, Temp ← 100] = {
Vdd: node;
powerSupply: voltage[Vdd, Gnd] = 5.0;
! ThymeBasics.thy
! CMOS2.0u100C.thy
Word line
PhBb, NotWord, NotWord1, Word, VGnd: node;
VGndSupply: voltage[VGnd, Gnd] = 0.0;
Q1: CTran[PhBb, Vdd, NotWord | W ← 10];
Q2: ETran[Vdd, NotWord, NotWord1 | W ← 10];
Q3: ETran[PhBb, NotWord1, VGnd | W ← 10];
Q4: CTran[NotWord, Vdd, Word | W ← 60];
Q5: ETran[NotWord, Word, VGnd | W ← 30];
C1: capacitor[Word, Gnd] = 6.71pF;
?: RectWave[PhBb | period ← 100ns, width ← 50ns, tRise ← 10ns, tFall ← 10ns];
};
IC[0, Vdd ← 5.0, NotWord ← 5.0, NotWord1 ← 5.0];
PLOT["CrossRAM word line", :1ns, -1, 6, PhBb, NotWord, NotWord1, Word, powerSupply^:-1.0mA, VGndSupply^:1.0mA];
RUN[tMax ← 100ns];