
    <<CrossRAMRoseTest.mesa>>
    <<Last edited by Barth, March 15, 1985 3:33:59 pm PST>>


    DIRECTORY
        BitOps, CrossRAM, RoseCreate, RoseRun, RoseTypes;

    CrossRAMRoseTest: CEDAR PROGRAM
        IMPORTS BitOps, RoseCreate, RoseRun
        SHARES CrossRAM =

    BEGIN OPEN
        CrossRAM;

    CrossRAMTestWrite2Read2: RoseTypes.CellTestProc =
        BEGIN
        instructions: CrossRAMIORef _ NARROW[io];
        drive: CrossRAMDriveRef _ NARROW[driveAsAny];
            BEGIN OPEN instructions;

            AccessRAM: PROC [write: BOOL, address: CARDINAL, data: LONG CARDINAL, parity: CARDINAL] = {
            d: BitOps.BitDWord _ BitOps.ILID[data, BitOps.BitDWordZero, 32, 0, 32];

            Address _ address;
            <<>>
            <<precharge>>
            nPrecharge _ FALSE;
            [] _ RoseRun.Eval[handle];
            nPrecharge _ TRUE;
            [] _ RoseRun.Eval[handle];
            <<>>
            <<enable select line>>
            Access _ TRUE;
            <<>>
            <<if write then enable write drivers>>
            IF write THEN {
            drive.s[Data] _ Drive;
            drive.s[Parity] _ Drive;
            Write _ TRUE;
            } ELSE {
            drive.s[Data] _ Test;
            drive.s[Parity] _ Test;
            Read _ TRUE;
            };
            Data _ d;
            Parity _ parity;
            [] _ RoseRun.Eval[handle];
            <<>>
            <<disable select line>>
            Access _ Write _ Read _ FALSE;
            <<>>
            drive.s[Data] _ Ignore;
            drive.s[Parity] _ Ignore;

            [] _ RoseRun.Eval[handle];
            };

            Vdd _ TRUE; Gnd _ FALSE; PadVdd _ TRUE; PadGnd _ FALSE;
            drive.s[Vdd] _ Drive; drive.s[Gnd] _ Drive;
            drive.s[PadVdd] _ Drive; drive.s[PadGnd] _ Drive;
            nPrecharge _ TRUE; Access _ FALSE; Write _ FALSE; Read _ FALSE;
            drive.s[nPrecharge] _ Drive; drive.s[Access] _ Drive;
            drive.s[Write] _ Drive; drive.s[Read] _ Drive;
            drive.s[Address] _ Drive;
            drive.s[Data] _ Ignore; drive.s[Parity] _ Ignore;
            AccessRAM[write: TRUE, address: 0, data: 0, parity: 0];
            AccessRAM[write: TRUE, address: 1, data: LAST[LONG CARDINAL], parity: 1];
            AccessRAM[write: FALSE, address: 0, data: 0, parity: 0];
            AccessRAM[write: FALSE, address: 1, data: LAST[LONG CARDINAL], parity: 1];
            END;
        END;

    ctest: RoseTypes.CellTest _ NEW[RoseTypes.CellTestRep _ ["Write2Read2", CrossRAMTestWrite2Read2, FALSE]];
    ct: RoseTypes.CellType _ RoseCreate.GetCellType["CrossRAM"];
    [] _ RoseCreate.SetTest[ctest, ct, TRUE];

    END.