AccessRAM:
PROC [write:
BOOL, address:
CARDINAL, data:
LONG
CARDINAL, parity:
CARDINAL] = {
d: BitOps.BitDWord ← BitOps.ILID[data, BitOps.BitDWordZero, 32, 0, 32];
Address ← address;
precharge
nPrecharge ← FALSE;
[] ← RoseRun.Eval[handle];
nPrecharge ← TRUE;
[] ← RoseRun.Eval[handle];
enable select line
Access ← TRUE;
if write then enable write drivers
IF write
THEN {
drive.s[Data] ← Drive;
drive.s[Parity] ← Drive;
Write ← TRUE;
}
ELSE {
drive.s[Data] ← Test;
drive.s[Parity] ← Test;
Read ← TRUE;
};
Data ← d;
Parity ← parity;
[] ← RoseRun.Eval[handle];
disable select line
Access ← Write ← Read ← FALSE;
drive.s[Data] ← Ignore;
drive.s[Parity] ← Ignore;
[] ← RoseRun.Eval[handle];
};
Vdd ← TRUE; Gnd ← FALSE; PadVdd ← TRUE; PadGnd ← FALSE;
drive.s[Vdd] ← Drive; drive.s[Gnd] ← Drive;
drive.s[PadVdd] ← Drive; drive.s[PadGnd] ← Drive;
nPrecharge ← TRUE; Access ← FALSE; Write ← FALSE; Read ← FALSE;
drive.s[nPrecharge] ← Drive; drive.s[Access] ← Drive;
drive.s[Write] ← Drive; drive.s[Read] ← Drive;
drive.s[Address] ← Drive;
drive.s[Data] ← Ignore; drive.s[Parity] ← Ignore;
AccessRAM[write: TRUE, address: 0, data: 0, parity: 0];
AccessRAM[write: TRUE, address: 1, data: LAST[LONG CARDINAL], parity: 1];
AccessRAM[write: FALSE, address: 0, data: 0, parity: 0];
AccessRAM[write: FALSE, address: 1, data: LAST[LONG CARDINAL], parity: 1];