CrossRAMPairDecoder.thy
Last Edited by: Barth, October 4, 1984 3:34:06 pm PDT
CIRCUIT[Lambda ← 1, Temp ← 100] = {
Vdd: node;
powerSupply: voltage[Vdd, Gnd] = 5.0;
! ThymeBasics.thy
! CMOS2.0u100C.thy
Address, Decode, D1, D2, D3, D4, D5, D6, D7: node;
Q11: CTran[Address, Vdd, Decode | W ← 3];
Q12: CTran[Address, Vdd, Decode | W ← 3];
Q13: CTran[Address, Vdd, Decode | W ← 3];
Q14: CTran[Address, Vdd, Decode | W ← 3];
Q15: CTran[Address, Vdd, Decode | W ← 3];
Q16: CTran[Address, Vdd, Decode | W ← 3];
Q17: CTran[Address, Vdd, Decode | W ← 3];
Q18: CTran[Address, Vdd, Decode | W ← 3];
Q21: ETran[Address, Decode, D1 | W ← 7];
Q22: ETran[Address, D1, D2 | W ← 7];
Q23: ETran[Address, D2, D3 | W ← 7];
Q24: ETran[Address, D3, D4 | W ← 7];
Q25: ETran[Address, D4, D5 | W ← 7];
Q26: ETran[Address, D5, D6 | W ← 7];
Q27: ETran[Address, D6, D7 | W ← 7];
Q28: ETran[Address, D7, Gnd | W ← 7];
Q29: ETran[Decode, Gnd, Gnd | W ← 10];
?: RectWave[Address | period ← 100ns, width ← 50ns, tRise ← 10ns, tFall ← 10ns];
};
IC[0, Vdd ← 5.0, Decode ← 5.0, D1 ← 5.0, D2 ← 5.0, D3 ← 5.0, D4 ← 5.0, D5 ← 5.0, D6 ← 5.0, D7 ← 5.0];
PLOT["CrossRAM decoder", :1ns, -1, 6, Address, Decode, D1, D2, D3, D4, D5, D6, D7];
RUN[tMax ← 100ns];