CrossRAMBitLineStatic.thy
Last Edited by: Barth, October 8, 1984 3:38:55 pm PDT
CIRCUIT[Lambda ← 1, Temp ← 100] = {
Vdd: node;
powerSupply: voltage[Vdd, Gnd] = 5.0;
! ThymeBasics.thy
! CMOS2.0u100C.thy
Bit Line
Word, nPrecharge, State, nState, Bit, nBit, VGnd, Sense: node;
VGndSupply: voltage[VGnd, Gnd] = 0.0;
QP1: CTran[State, Vdd, nState | W ← 3, L ← 5];
QP2: CTran[nState, Vdd, State | W ← 3, L ← 5];
Q1: ETran[Word, Bit, State | W ← 4];
Q2: ETran[State, nState, VGnd | W ← 7];
Q3: ETran[nState, State, VGnd | W ← 7];
Q4: ETran[Word, nBit, nState | W ← 4];
Q5: CTran[nPrecharge, Bit, Vdd | W ← 8];
Q6: CTran[nPrecharge, nBit, Vdd | W ← 8];
Q7: CTran[nBit, Vdd, Sense | W ← 8];
Q8: ETran[nBit, Sense, Gnd | W ← 4];
C1: capacitor[Bit, Gnd] = 2.44pF;
C2: capacitor[nBit, Gnd] = 2.44pF;
C3: capacitor[Sense, Gnd] = 0.1pF;
?: RectWave[Word | period ← 100ns, width ← 50ns, tRise ← 10ns, tFall ← 10ns, tDelay ← 50ns];
?: RectWave[nPrecharge | OnLevel ← 0V, OffLevel ← 5V, period ← 100ns, width ← 50ns, tRise ← 10ns, tFall ← 10ns];
};
IC[0, Vdd ← 5.0, State ← 3.3, nState ← 0.0];
PLOT["CrossRAM bit line", :1ns, -1, 6, Word, nPrecharge, State, nState, Bit, nBit, Sense, powerSupply^:-1.0mA, VGndSupply^:0.1mA];
RUN[tMax ← 100ns];