CrossRAMAnd3.thy
Last Edited by: Barth, October 5, 1984 2:47:33 pm PDT
CIRCUIT[Lambda ← 1, Temp ← 100] = {
Vdd: node;
powerSupply: voltage[Vdd, Gnd] = 5.0;
! ThymeBasics.thy
! CMOS2.0u100C.thy
Address Driver
AddressIn, nAddressIn, NAnd1, NAnd2, NAnd, And, VGnd: node;
VGndSupply: voltage[VGnd, Gnd] = 0.0;
Q1: CTran[AddressIn, Vdd, nAddressIn | W ← 16];
Q2: ETran[AddressIn, nAddressIn, VGnd | W ← 8];
Q3: CTran[nAddressIn, Vdd, NAnd | W ← 16];
Q4: CTran[Vdd, Vdd, NAnd | W ← 16];
Q5: CTran[Vdd, Vdd, NAnd | W ← 16];
Q6: ETran[nAddressIn, NAnd, NAnd1 | W ← 16];
Q7: ETran[Vdd, NAnd1, NAnd2 | W ← 16];
Q8: ETran[Vdd, NAnd2, VGnd | W ← 16 ];
Q9: CTran[NAnd, Vdd, And | W ← 32];
Q10: ETran[NAnd, And, VGnd | W ← 16];
C1: capacitor[And, Gnd] = 3.09pF;
C2: capacitor[nAddressIn, Gnd] = 0.387pF;
?: RectWave[AddressIn | period ← 100ns, width ← 50ns, tRise ← 10ns, tFall ← 10ns, tDelay ← 20ns];
};
PLOT["CrossRAM Address Driver", :1ns, -1, 6, AddressIn, nAddressIn, NAnd1, NAnd2, NAnd, And, powerSupply^:-0.5mA, VGndSupply^:0.5mA];
RUN[tMax ← 100ns];