<> <> CIRCUIT[Lambda _ 1, Temp _ 100] = { Vdd: node; powerSupply: voltage[Vdd, Gnd] = 5.0; ! ThymeBasics.thy ! CMOS2.0u100C.thy <

> <<>> AddressIn, nAddressIn, AddressToDecoder, nAddressToDecoder, VGnd: node; VGndSupply: voltage[VGnd, Gnd] = 0.0; Q1: CTran[AddressIn, Vdd, nAddressIn | W _ 8]; Q2: ETran[AddressIn, nAddressIn, VGnd | W _ 4]; Q3: CTran[AddressIn, Vdd, nAddressToDecoder | W _ 32]; Q4: ETran[AddressIn, nAddressToDecoder, VGnd | W _ 16]; Q5: CTran[nAddressIn, Vdd, AddressToDecoder | W _ 32]; Q6: ETran[nAddressIn, AddressToDecoder, VGnd | W _ 16]; C1: capacitor[AddressToDecoder, Gnd] = 2.59pF; C2: capacitor[nAddressToDecoder, Gnd] = 2.59pF; ?: RectWave[AddressIn | period _ 100ns, width _ 50ns, tRise _ 10ns, tFall _ 10ns, tDelay _ 20ns]; <<>> }; PLOT["CrossRAM Address Driver", :1ns, -1, 6, AddressIn, nAddressIn, AddressToDecoder, nAddressToDecoder, powerSupply^:-0.5mA, VGndSupply^:0.5mA]; RUN[tMax _ 100ns];