Address Driver
AddressIn, nAddressIn, AddressToDecoder, nAddressToDecoder, VGnd: node;
VGndSupply: voltage[VGnd, Gnd] = 0.0;
Q1: CTran[AddressIn, Vdd, nAddressIn | W ← 8];
Q2: ETran[AddressIn, nAddressIn, VGnd | W ← 4];
Q3: CTran[AddressIn, Vdd, nAddressToDecoder | W ← 32];
Q4: ETran[AddressIn, nAddressToDecoder, VGnd | W ← 16];
Q5: CTran[nAddressIn, Vdd, AddressToDecoder | W ← 32];
Q6: ETran[nAddressIn, AddressToDecoder, VGnd | W ← 16];
C1: capacitor[AddressToDecoder, Gnd] = 2.59pF;
C2: capacitor[nAddressToDecoder, Gnd] = 2.59pF;
?: RectWave[AddressIn | period ← 100ns, width ← 50ns, tRise ← 10ns, tFall ← 10ns, tDelay ← 20ns];