The RAM has a 33 bit data bus, intended to be used for a 32 bit data word plus parity. It has an 11 bit address bus, the 3 low order bits select a word within a row of the RAM and the 8 high order bits select which row of the RAM is accessed. There are 4 control pins: Read, Write, Access and Precharge. Read and Write should be exclusive, i.e. never asserted as the same time, as should Access and Precharge. The Write pin controls the drivers which swing the bit lines within the RAM. Precharge forces the bit lines high. Since there is no interlock within the chip to prevent Precharge and Write from going high at the same time care should be taken externally to ensure that they don't.

The RAM cell contains the bit array and the precharge circuit.

The precharge circuit is just a set of transistors that restores the bit lines to the power supply between each cycle.

The RAM bit cell is a 2147H static ram cell (more or less) with the pullups removed. It would be nice if the RAM cell could be made static but with the technology we currently have that would cost about a factor of 2 in density. A high resistivity poly layer or buried contacts on both sides of the well would make the price of static memory less.

The layout of the RAM cell determines the layout and circuit design of the rest of the circuit. There are several factors to consider while designing this cell:

First lets consider the access transistor size. Most of the bit line capacitance comes from the diffusion capacitance associated with the bit line metal to diffusion contact and the access transistor channel extension. To minimize bit line capacitance requires making the access transistor as small as possible. To maximize drive capability requires making it as large as possible. Since each word on a bit line requires the access transistor, making the transistor n times larger only increases the drive capability by n while increasing the loading by the number of words times n, in this case 256n. This argues for making the transistor as small as possible. However there is another limitation and that is the size of the metal to diffusion contact to which the access transistor is connected. Making the access transistor smaller than such a contact does not improve the capacitance situation much but does decrease the drive capability significantly. Thus the size of the access transistors are matched to the size of a metal-diffusion contact.

Next consider the flip flop transitor sizes. This is easy since the cell gets more drive capability and storage capability as the size of these transistors grow. Thus they should be made as big as possible while still achieving whatever density goals have been set for the RAM. Best information available suggests that an alpha particle hit generates about 1 million electron hole pairs. The current capacitor in the cell only stores about half that number so the soft error rate will depend on how efficiently the cell collects the charge generated by an alpha hit. The error rate will be a measured parameter after building the chip since I do not know any way to model the collection efficiency.

Discussion of providing a good ground plane is deferred to the section on power bus sizing.

The cell layout gives the following capacitances:

From this simulation we can see that the precharge transistors are quite adequate. The two currents indicate what the peak currents will be. They will be useful later for determining the power bus widths. The simulations for worst case power supply current should really be run at zero degress Celsius and with fast transistor parameters but since no such data exist for the process yet we shall not bother with these additional simulations.

If we use midpoint values to calculate delays then the access time of the array itself, measured from midpoint of the word line to midpoint of the bit line, is about 20ns. Also we can see that the state nodes in the RAM cell bounce about a bit during the access but they end up at the same point that they started at. The initial condition used for the high state bit was selected by successive approximation. Alternatively one could simply run the simulation for a number of cycles and determine the steady state value from that.

The decoder consists of:

This is a simulation of the NAnd gate. The simulation says that the output pretty much tracks the address inputs when the address has a 10ns edge. One amusing thing to worry about is the intermediate nodes in the stack of N channel transistors. Since there are generally no restrictions on how the address lines may flap prior to stabilizing at the setup time before the access clock it is possible to capacitively pump these nodes to voltages that inject charge into the substrate. There are guard bands around the NAnd gate to protect against latchup due to this.

This simulation determines the size of the word line driver transistors. I merely attempted to keep the slope of the output waveform equal to the slope of the input waveform.

The data buffer consists of a multiplexor and three tristate buffers. Two of the buffers are used to drive true and complement data onto the bit lines during a write cycle. The other is used to drive data back to the pads during a read cycle. The multiplexor selects one word out of the eight words in a RAM row. Since the access transistors in the RAM cell are only N channel the multiplexor need only have N channel transistors rather than both N and P channel. However there really should be a precharge transistor on the nodes between the multiplexor and the write buffers so that during a read cycle the buffer which sends data to the pads sees a good one rather than a voltage which is one threshold below the power supply.

The size of the tristate buffer transistors and the multiplexor transistor are determined from this simulation. The inverter size was simply chosen to be the minimum. This is also where the worst case ground current occurs.

There are three different pads that handle logic signals. All of them have the protection devices and level shifter shown in Basic Pad. Input Pad merely buffers the signal one more stage. Differential Input Pad supplies both true and complement forms of the input signal. The Bidirectional Pad has two levels of output amplification and a single stage of amplification from the level shifter to the internal data bus.

The input simulation is used to determine what ratio is adequate to shift TTL levels to CMOS levels. It also determines the size of the buffer needed to drive the internal data bus. The capacitance of the internal data bus is:

This simulation is used to decide how large the output transistors should be. It is also used for determining how large the power bus that runs around the pad ring needs to be.

The low order 3 bits are inverted and then demultiplexed into eight seperate select lines that run the word select multiplexor in the data buffer. The other 8 bits are buffered and sent in differential form into the decoder.

The capacitance of an address line is:

The capacitance of a select line is:

The capacitance of an address inverter line is:

The size of a ground line through the array was fixed by the cell layout. Only major problems should be allowed to perturb the size of this line since it impacts the overall size of the chip so significantly.

The lengths of the ground buses, in microns, are:

The currents through the branches of the ground network are:

The voltage change from the pc board to the bonding pad due to inductance is:

Given the currents in the segments and the segment lengths we can pick segment widths such that the maximum voltage change is less than 0.75 volt. Assume that the voltage drop per unit length of wire should be constant. Then DVsegment ← a Lsegment.

We want the maximum of [VAddress Drivers, VData Buffer, VDecoder, VRAM] to be equal to 0.75 volts. This is easy if we just assume that one of these, e.g. VRAM, is the worst case, use it to compute a and then just check the others.

The layout would be better if WG1-3 were all 96. If they were what would WG RAM have to be?

Now what should the width of the other ground lines be?

From the big change in the Address Driver width we can see that applying the assumption of uniform voltage drop per unit length to different paths of the tree leads to buses that are much too wide for the shorter stubs.

Here we don't much care how far up the ground plane bounces nor how far down the Vdd plane bounces. We do care if they ring more than a diode threshold above the power supply or below ground since that can inject charge into the substrate and cause latchup.

The output simulation indicates that each output pad requires a peak of 40mA through the Vdd plane and 45mA through the ground plane. Di/dt for each are 40mA/5ns, or 8.0e+6 A/s, and 45mA/5ns, or 9.0e+6 A/s respectively. Assume 5nH of inductance in a single pin and 7 power pins per supply. Then the ground plane will spike by .212 volts ← (5e-9/7) * (33 * 9.0e+6). This seems just fine.

The maximum distance from any output pad to a Vdd or ground pad is 3.6mm. The width of these buses is 60m. This gives a resistance of 3.6 ← 0.06*3.6e-3/60e-6, and at 45mA, a voltage drop of 1.29 volts ← 8*45e-3*3.6, assuming that there are 8 output pads along the way.

The preceding analysis totally ignores electromigration because I am assuming that the huge buses that the IR drop calculations call for will excede the bus widths called for because of electromigration. The tedious but straightforward nature of the analysis cries out for automation. The assumed noise margins of 0.75 volts in the internal ground plane and 1 volt in the internal Vdd plane were pulled more or less out of thin air and no analysis of the impact on performance has been done. I believe it is true that almost any amount of bounce in the Vdd plane, or up to 2 volts of bounce in the ground plane, can be tolerated without losing data, although the performance will suffer. Beyond 2 volts of bounce in the ground plane will cause charge to be dumped into unselected words of the RAM and cause their state to be lost.

It is probably true that there should be multiple internal power pads for a design such as this. Splitting the external power pads into several sections should be not harm anything and that would allow the internal pads to be spaced around the chip, thereby reducing the ridiculously large, although possibly still inadequate, power buses that were used in this design. Since the inductive rise is so small, fewer pads for the output drivers would be ok anyway.

Since I last updated this document I have run the chip through the Chipmonk design rule check and circuit extract program. Unfortunately it blows up after it has started extracting the main memory array. I ended up rotating the chip three times and checking it from each of the four edges. I hope that no errors were missed because of dangling nodes that might become connected. Also since the program could not extract the circuit there is no way to run Crystal or to run the layout through a switch level simulator.

The RAM is due out of the processing line 2/7. The tester is up to the point that building scope loops is easy. It appears that most of the code and hardware needed to send long sequences of vectors is in place. Still have to build a refresh circuit and a trigger circuit. The trigger circuit should have go conditioned either by global hold or global hold bar. Should put some known working rams in the socket to perform a final test of the test setup prior to testing real circuits. Should also get rid of the 1V undershoot on the channel chip outputs.

An interesting set of numbers for taps are: 0, 60, 25, 7, 35, 2, 53, 52, 3, 1, 56.

Silicided single level parts were delivered Friday, 15 February.

The tester was brought up to the point of testing a Hitachi 6116 2Kx8 static RAM a week or two ago. One problem still remains with the testing of that part. If the default address that is supplied when no read or write cycles occur is set to zero then spurious errors occur in some of the bits. If the default address is all ones then no errors occur.

They are having trouble bonding CrossRAM parts because the balls at the end of the bonds are going beyond the design rule distance to unrelated circuitry. That might not be a problem with passivated parts.

Optical inspection reveals the following:

A quality order is then A, E, B, D, C.

M. Overton rebuilt the power supply cable to the RAM. It had 3 volts of noise on both the Vdd and Gnd supplies. Unifying the ground plane with the wire wrap ground plane and bypassing the Vdd lines directly to that ground plane cleaned things up substantially.

Alternating address bits have their true and complement values reversed. The leftmost bit as the order (true, complement). The next has order (complement, true). This requires a change to the data pattern and error bit map procedures.

The node which drives the word line buffers sinks rather rapidly when the access clock goes high and the word is not selected. Turning off the light had no effect. I suspect that the silicide leakage problem has struck again.

The precharge pad is noninverting. It directly feeds the p channel transistors which pull up the bit lines. This means precharge is asserted low rather than high so I need to flip the test program about.

Silicide single level metal chips.

The mystery of the day is why a gray pattern appears over several passes. There are random single bit failures in several, if not all, chips.

During testing of the poly chips something shorted and started melting the socket. C did the melting, D felt hot so I removed it quickly, then I inserted A, it appeared to work the same as when I first tested it then, just as I was about to remove it, it became very hot and started getting lots of errors. Is this latchup in action?

Should put the device under test on a seperate power supply with a current limit just above what the chip nominally takes. Need to slow down the tester. Replace the crystal with a pulse generator and/or make each RAM cycle take multiple tester cycles by changing the CycleRAM code. Need to confirm the address mapping from silicon to bit map.

DLM/Polycide A, B and C appear to have shorts. The data line gets clamped and the inputs are degraded. DLM/Poly A shows no signs of life but is not shorted, B gets the scope loop right but the error map appears to only have working bits where the DLM word lines strap to the poly, C almost gets the scope loop right, but not quite.

It has been decided that the risks associated with a dynamic RAM are too large. Use of a static RAM makes buried contacts unnecessary. The second version of the RAM eliminates buried contacts and is half static. The dynamic portion has been kept to check for leakage problems in processing.