<> <> Imports BitOps, RoseRun, RoseTypes; Library Pads; <> Cedar CrossRAMWord: TYPE = RECORD[ data: BitOps.BitDWord, parity: BitOps.BitWord ]; ; CrossAddressPads: InputPadSequence[count: 11]; CrossDataPads: BidirectionalPadSequence[count: 33]; CrossDataBuffer: DataBufferSequence[count: 33]; CrossRAMArray: RAMArray[rows: 256, columns: 264, pullUpStrength: none]; CELLTYPE "CrossRAM" PORTS [Vdd, Gnd, PadVdd, PadGnd, nPrecharge, Access, Write, Read> <> nPrecharge _ FALSE; [] _ RoseRun.Eval[handle]; nPrecharge _ TRUE; [] _ RoseRun.Eval[handle]; <<>> <> Access _ TRUE; <<>> <> IF write THEN { drive[Data] _ drive; drive[Parity] _ drive; Write _ TRUE; } ELSE { drive[Data] _ test; drive[Parity] _ test; Read _ TRUE; }; Data _ d; Parity _ parity; [] _ RoseRun.Eval[handle]; <<>> <> Access _ Write _ Read _ FALSE; <<>> drive[Data] _ ignore; drive[Parity] _ ignore; [] _ RoseRun.Eval[handle]; }; Vdd _ TRUE; Gnd _ FALSE; PadVdd _ TRUE; PadGnd _ FALSE; drive[Vdd] _ drive; drive[Gnd] _ drive; drive[PadVdd] _ drive; drive[PadGnd] _ drive; nPrecharge _ TRUE; Access _ FALSE; Write _ FALSE; Read _ FALSE; drive[nPrecharge] _ drive; drive[Access] _ drive; drive[Write] _ drive; drive[Read] _ drive; drive[Address] _ drive; drive[Data] _ ignore; drive[Parity] _ ignore; [] _ RoseRun.Eval[handle ! RoseTypes.Stop => IF data=$FailedAssertion THEN CONTINUE ]; AccessRAM[write: TRUE, address: 0, data: 0, parity: 0]; AccessRAM[write: TRUE, address: 1, data: LAST[LONG CARDINAL], parity: 1]; AccessRAM[write: FALSE, address: 0, data: 0, parity: 0]; AccessRAM[write: FALSE, address: 1, data: LAST[LONG CARDINAL], parity: 1]; ENDCELLTYPE