<> <> <> DIRECTORY Core, CrossRAM, IO, Pads, SSI; CrossRAMImpl: CEDAR PROGRAM IMPORTS Core, IO, Pads, SSI EXPORTS CrossRAM = BEGIN OPEN Core, CrossRAM; CreateCrossRAM: PUBLIC PROC [design: Design] RETURNS [ct: CellType] = { name: ROPE _ "CrossRAM"; <> { bus8: NetType _ CreateSequenceNetType[design: design, count: 8]; bus11: NetType _ CreateSequenceNetType[design: design, count: 11]; bus33: NetType _ CreateSequenceNetType[design: design, count: 33]; bus256: NetType _ CreateSequenceNetType[design: design, count: 256]; bus264: NetType _ CreateSequenceNetType[design: design, count: 264]; ct _ CreateCellType[design: design, cellTypeName: name]; CreateNet[in: ct, name: "nPrechargeB"]; CreateNet[in: ct, name: "AccessB"]; CreateNet[in: ct, name: "WriteB"]; CreateNet[in: ct, name: "nWriteB"]; CreateNet[in: ct, name: "ReadB"]; CreateNet[in: ct, name: "nReadB"]; CreateNet[in: ct, name: "AddressB", type: bus11]; CreateNet[in: ct, name: "DataB", type: bus33]; CreateNet[in: ct, name: "Select", type: bus8]; CreateNet[in: ct, name: "AdrBits", type: bus8]; CreateNet[in: ct, name: "nAdrBits", type: bus8]; CreateNet[in: ct, name: "Word", type: bus256]; CreateNet[in: ct, name: "Bits", type: bus264]; CreateNet[in: ct, name: "nBits", type: bus264]; CreateCrossRAMPads[design: design, ct: ct]; CreateCell[in: ct, type: CreateCrossRAMAddressSSI[design: design]]; <> <> <> }; }; CreateCrossRAMPads: PROC [design: Design, ct: CellType] = { bus11: NetType _ CreateSequenceNetType[design: design, count: 11]; bus33: NetType _ CreateSequenceNetType[design: design, count: 33]; inputPad: CellType _ Pads.CreateInputPad[design: design]; differentialInputPad: CellType _ Pads.CreateDifferentialInputPad[design: design]; bidirectionalPad: CellType _ Pads.CreateBidirectionalPad[design: design]; CreatePort[on: ct, name: "Vdd"]; CreatePort[on: ct, name: "Gnd"]; CreatePort[on: ct, name: "PadVdd"]; CreatePort[on: ct, name: "PadGnd"]; CreatePort[on: ct, name: "nPrecharge"]; CreatePort[on: ct, name: "Access"]; CreatePort[on: ct, name: "Write"]; CreatePort[on: ct, name: "Read"]; CreatePort[on: ct, name: "Address", type: bus11]; CreatePort[on: ct, name: "Data", direction: bidirectional, type: bus33]; CreateCell[in: ct, type: inputPad, bind: "Vdd: PadVdd, Gnd: PadGnd, Pad: nPrecharge, Output: nPrechargeB"]; CreateCell[in: ct, type: inputPad, bind: "Vdd: PadVdd, Gnd: PadGnd, Pad: Access, Output: AccessB"]; CreateCell[in: ct, type: differentialInputPad, bind: "Vdd: PadVdd, Gnd: PadGnd, Pad: Write, Output: WriteB, nOutput: nWriteB"]; CreateCell[in: ct, type: differentialInputPad, bind: "Vdd: PadVdd, Gnd: PadGnd, Pad: Read, Output: ReadB, nOutput: nReadB"]; FOR addressPad: [0..11) IN [0..11) DO CreateCell[in: ct, type: inputPad, bind: IO.PutFR["Vdd: PadVdd, Gnd: PadGnd, Pad: Address[%g], Output: AddressB[%g]", IO.int[addressPad], IO.int[addressPad]]]; ENDLOOP; FOR dataPad: [0..33) IN [0..33) DO CreateCell[in: ct, type: bidirectionalPad, bind: IO.PutFR["Vdd: PadVdd, Gnd: PadGnd, Read: ReadB, nRead: ReadB, Write: WriteB, nWrite: nWriteB, Pad: Data[%g], Data: DataB[%g]", IO.int[dataPad], IO.int[dataPad]]]; ENDLOOP; }; CreateCrossRAMAddressSSI: PROC [design: Design] RETURNS [ct: CellType] = { bus3: NetType _ CreateSequenceNetType[design: design, count: 3]; bus8: NetType _ CreateSequenceNetType[design: design, count: 8]; bus11: NetType _ CreateSequenceNetType[design: design, count: 11]; invert8: CellType _ SSI.CreateInverter[design: design, width: 8]; and3: CellType _ SSI.CreateAnd[design: design, inputCount: 3, width: 16]; decoderDriver: CellType _ CreateDecoderDriver[design: design]; ct _ CreateCellType[design: design, cellTypeName: "CrossRAMAddressSSI"]; CreatePort[on: ct, name: "Vdd"]; CreatePort[on: ct, name: "Gnd"]; CreatePort[on: ct, name: "AddressB", type: bus11]; CreatePort[on: ct, name: "Select", type: bus8, direction: output]; CreatePort[on: ct, name: "AdrBits", type: bus8, direction: output]; CreatePort[on: ct, name: "nAdrBits", type: bus8, direction: output]; CreateNet[in: ct, name: "nHighAddressB", type: bus3]; CreateCell[in: ct, type: invert8, bind: "Input: Address[8], Output: nHighAddressB[0]"]; CreateCell[in: ct, type: invert8, bind: "Input: Address[9], Output: nHighAddressB[1]"]; CreateCell[in: ct, type: invert8, bind: "Input: Address[10], Output: nHighAddressB[2]"]; <> <> <> FOR adrBit: CARDINAL IN [3..11) DO CreateCell[in: ct, type: decoderDriver, bind: IO.PutFR["Address: AddressB[%g], AdrBit: AdrBit[%g], nAdrBit: nAdrBit[%n]", IO.int[adrBit], IO.int[adrBit], IO.int[adrBit]]]; ENDLOOP; }; CreateDecoderDriver: PROC [design: Design] RETURNS [ct: CellType] = { invert4: CellType _ SSI.CreateInverter[design: design, width: 4]; invert16: CellType _ SSI.CreateInverter[design: design, width: 16]; ct _ CreateCellType[design: design, cellTypeName: "DecoderDriver"]; CreatePort[on: ct, name: "Vdd"]; CreatePort[on: ct, name: "Gnd"]; CreatePort[on: ct, name: "Address"]; CreatePort[on: ct, name: "AdrBit", direction: output]; CreatePort[on: ct, name: "nAdrBit", direction: output]; CreateNet[in: ct, name: "nAddress"]; CreateCell[in: ct, type: invert4, bind: "Input: Address, Output: nAddress"]; CreateCell[in: ct, type: invert16, bind: "Input: nAddress, Output: AdrBit"]; CreateCell[in: ct, type: invert16, bind: "Input: Address, Output: nAdrBit"]; }; END.